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Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity

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Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity

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Title: Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
Author: Yu, Hao; Ho, Joanna; He, Lei
Copyright year: 2009
Abstract: The existing work on via allocation in 3D ICs ignores power/ground vias’ ability to simultaneously reduce voltage bounce and remove heat. This paper develops the first in-depth study on the allocation of power/ground vias in 3D ICs with simultaneous consideration of power and thermal integrity. By identifying principal ports and parameters, effective electrical and thermal macromodels are employed to provide dynamic power and thermal integrity as well as sensitivity with respect to via density. With the use of sensitivity, an efficient via allocation simultaneously driven by power and thermal integrity is developed. Experiments show that compared to sequential power and thermal optimization using static integrity, sequential optimization using the dynamic integrity reduces non-signal vias by up to 18%, and simultaneous optimization using dynamic integrity further reduces non-signal vias by up to 45.5%.
Subject: DRNTU::Engineering::Electrical and electronic engineering.
Type: Journal Article
Series/ Journal Title: ACM transactions on design automation of electronic systems
School: School of Electrical and Electronic Engineering
Rights: © 2009 ACM. This is the author created version of a work that has been peer reviewed and accepted for publication by ACM Transactions on Design Automation of Electronic Systems, ACM. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1145/1529255.1529263].
Version: Accepted version

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