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Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity

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Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity

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dc.contributor.author Yu, Hao
dc.contributor.author Ho, Joanna
dc.contributor.author He, Lei
dc.date.accessioned 2012-10-10T07:51:16Z
dc.date.available 2012-10-10T07:51:16Z
dc.date.copyright 2009
dc.date.issued 2012-10-10
dc.identifier.citation Yu, H., Ho, J., & He, L. (2009). Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. ACM Transactions on Design Automation of Electronic Systems, 14(3).
dc.identifier.issn 1084-4309
dc.identifier.uri http://hdl.handle.net/10220/8745
dc.description.abstract The existing work on via allocation in 3D ICs ignores power/ground vias’ ability to simultaneously reduce voltage bounce and remove heat. This paper develops the first in-depth study on the allocation of power/ground vias in 3D ICs with simultaneous consideration of power and thermal integrity. By identifying principal ports and parameters, effective electrical and thermal macromodels are employed to provide dynamic power and thermal integrity as well as sensitivity with respect to via density. With the use of sensitivity, an efficient via allocation simultaneously driven by power and thermal integrity is developed. Experiments show that compared to sequential power and thermal optimization using static integrity, sequential optimization using the dynamic integrity reduces non-signal vias by up to 18%, and simultaneous optimization using dynamic integrity further reduces non-signal vias by up to 45.5%.
dc.language.iso en
dc.relation.ispartofseries ACM transactions on design automation of electronic systems
dc.rights © 2009 ACM. This is the author created version of a work that has been peer reviewed and accepted for publication by ACM Transactions on Design Automation of Electronic Systems, ACM. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1145/1529255.1529263].
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1145/1529255.1529263
dc.description.version Accepted version
dc.identifier.rims 148332

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