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An EScheduler-based data dependence analysis and task scheduling for parallel circuit simulation

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An EScheduler-based data dependence analysis and task scheduling for parallel circuit simulation

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dc.contributor.author Chen, Xiaoming
dc.contributor.author Wu, Wei
dc.contributor.author Wang, Yu
dc.contributor.author Yu, Hao
dc.contributor.author Yang, Huazhong
dc.date.accessioned 2012-10-10T08:55:03Z
dc.date.available 2012-10-10T08:55:03Z
dc.date.copyright 2011
dc.date.issued 2012-10-10
dc.identifier.citation Chen, X., Wu, W., Wang, Y., Yu, H., & Yang, H. (2011). An EScheduler-based data dependence analysis and task scheduling for parallel circuit simulation. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(10), 702-706.
dc.identifier.uri http://hdl.handle.net/10220/8748
dc.description.abstract The sparse matrix solver has become the bottleneck in a Simulation Program with Integrated Circuit Emphasis circuit simulator. It is difficult to parallelize the sparse matrix solver because of the high data dependence during the numerical LU factorization. In this brief, a parallel LU factorization algorithm is developed on shared-memory computers with multicore central processing units, based on KLU algorithms. An Elimination Scheduler (EScheduler) is proposed to represent the data dependence during the LU factorization. Based on the EScheduler, the parallel tasks are scheduled in two modes to achieve a high level of concurrence, i.e., cluster mode and pipeline mode. The experimental results on 26 circuit matrices reveal that the developed algorithm can achieve speedup of 1.18–4.55× (on geometric average), as compared with KLU, with 1–8 threads. The result analysis indicates that for different data dependence, different parallel strategies should be dynamically selected to obtain optimal performance.
dc.language.iso en
dc.relation.ispartofseries IEEE transactions on circuits and systems II: express briefs
dc.rights © 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI: http://dx.doi.org/10.1109/TCSII.2011.2164148].
dc.subject DRNTU::Engineering::Electrical and electronic engineering.
dc.title An EScheduler-based data dependence analysis and task scheduling for parallel circuit simulation
dc.type Journal Article
dc.contributor.school School of Electrical and Electronic Engineering
dc.identifier.doi http://dx.doi.org/10.1109/TCSII.2011.2164148
dc.description.version Accepted version
dc.identifier.rims 162552

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