Showing results 34 to 53 of 85
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| Issue Date | Title | Author(s) |
| 2018 | A crosstalk-immune sub-THz All-surface-wave I/O transceiver in 65-nm CMOS | Liang, Yuan; Boon, Chirn Chye; Yu, Hao |
| 2018 | D-band surface-wave modulator and signal source with 40 dB extinction ratio and 3.7 mW output power in 65 nm CMOS | Liang, Yuan; Yu, Hao; Boon, Chirn Chye; Li, Chenyang; Kissinger, Dietmar; Wang, Yong |
| 2015 | Design and analysis of a K-band wideband voltage-controlled oscillator with robust start-up and frequency boost | Sun, Junyi; Boon, Chirn Chye; Yi, Xiang; Lim, Wei Meng; Meng, Fanyi |
| 2019 | Design and analysis of D-Band on-chip modulator and signal source based on split-ring resonator | Liang, Yuan; Boon, Chirn Chye; Li, Chenyang; Tang, Xiao-Lan; Ng, Herman Jalli; Kissinger, Dietmar; Wang, Yong; Zhang, Qingfeng; Yu, Hao |
| 2010 | Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler | Yeo, Kiat Seng; Boon, Chirn Chye; Lim, Wei Meng; Do, Manh Anh; Krishna, Manthena Vamshi |
| 2010 | Design of a CMOS broadband transimpedance amplifier with active feedback | Lu, Zhenghao; Yeo, Kiat Seng; Lim, Wei Meng; Do, Manh Anh; Boon, Chirn Chye |
| 2011 | Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit | Tan, Yung Sern; Yeo, Kiat Seng; Boon, Chirn Chye; Do, Manh Anh |
| 2020 | Design of a wideband variable-gain amplifier with self-compensated transistor for accurate dB-linear characteristic in 65 nm CMOS technology | Kong, Lingshan; Liu, Hang; Zhu, Xi; Boon, Chirn Chye; Li, Chenyang; Liu, Zhe; Yeo, Kiat Seng |
| 2012 | Design of quarter-wavelength resonator filters with coupling controllable paths | Meng, Fanyi; Ma, Kaixue; Xu, Shanshan; Yeo, Kiat Seng; Boon, Chirn Chye; Lim, Wei Meng; Do, Manh Anh |
| 2014 | Design of ultra-low phase noise and high power integrated oscillator in 0.25µm GaN-on-SiC HEMT technology | Liu, Hang; Zhu, Xi; Boon, Chirn Chye; Yi, Xiang; Mao, Mengda; Yang, Wanlan |
| 2011 | A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector | Tan, Yung Sern; Yeo, Kiat Seng; Boon, Chirn Chye; Do, Manh Anh |
| 2023 | A dual-path subsampling PLL with ring VCO phase noise suppression | Dong, Yangtao; Boon, Chirn Chye; Liu, Zhe; Yang, Kaituo |
| 2010 | An energy-aware CMOS receiver front end for low-power 2.4-GHz applications | Do, Aaron V.; Boon, Chirn Chye; Do, Manh Anh; Yeo, Kiat Seng; Cabuk, Alper |
| 2018 | A fully integrated Class-J GaN MMIC power amplifier for 5-GHz WLAN 802.11ax application | Liu, Bei; Mao, Mengda; Boon, Chirn Chye; Choi, Pilsoon; Khanna, Devrishi; Fitzgerald, Eugene A. |
| 2005 | Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction | Boon, Chirn Chye; Do, Manh Anh; Yeo, Kiat Seng; Ma, Jianguo |
| 2008 | Fully symmetrical monolithic transformer (true 1:1) for silicon RFIC | Lim, Chee Chong; Yeo, Kiat Seng; Chew, Kok Wai Johnny; Cabuk, Alper; Gu, Jiang Min; Lim, Suh Fei; Boon, Chirn Chye; Do, Manh Anh |
| 2009 | A fully-integrated low power PAM/PPM multi-channel UWB transmitter | Chen, Caixia; Do, Manh Anh; Yeo, Kiat Seng; Boon, Chirn Chye |
| 2012 | GaN-on-Silicon integration technology | Ng, Geok Ing; Arulkumaran, Subramaniam; Vicknesh, Sahmuganathan; Wang, H.; Ang, K. S.; Kumar, C. M. Manoj; Ranjan, K.; Lo, Guo-Qiang; Tripathy, Sudhiranjan; Boon, Chirn Chye; Lim, Wei Meng |
| 2018 | Heterogeneous integration of GaN and BCD technologies and its applications to high conversion-ratio DC-DC boost converter IC | Meng, Fanyi; Disney, Don; Liu, Bei; Volkan, Yildirim Baris; Zhou, Ao; Liang, Zhipeng; Yi, Xiang; Selvaraj, Susai Lawrence; Peng, Lulu; Ma, Kaixue; Boon, Chirn Chye |
| 2009 | High frequency drain current noise modeling in MOSFETs under sub-threshold condition | Chan, Lye Hock; Yeo, Kiat Seng; Chew, Kok Wai Johnny; Ong, Shih Ni; Loo, Xi Sung; Boon, Chirn Chye; Do, Manh Anh |