Showing results 15 to 27 of 27
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| Issue Date | Title | Author(s) |
 | 1996 | High-level synthesis of large digital systems based on precedence bipartite model | Shen Zhaoxuan. |
 | 2008 | High-speed and low-power serial accumulator for serial/parallel multiplier | Meher, Manas Ranjan; Jong, Ching Chuen; Chang, Chip Hong |
| | 2018 | A high-throughput VLSI architecture for real-time full-HD gradient guided image filter | Wu, Lei; Jong, Ching Chuen |
| 2001 | IC CAD & design automation | Jong, Ching Chuen |
| 2006 | Implementation of digital systems on FPGA devices | Chen, Lan. |
| 2003 | Investigation of design techniques to reduce glitches for low power | Foo, Chee Yin. |
| | 2013 | A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT | Hu, Yusong; Jong, Ching Chuen |
| | 2013 | A memory-efficient scalable architecture for lifting-based discrete wavelet transform | Hu, Yusong; Jong, Ching Chuen |
| | 2013 | A memory-efficient tables-and-additions method for accurate computation of elementary functions | Low, Joshua Yung Lih; Jong, Ching Chuen |
| 2005 | Modeling of PCI with SystemVerilog | Chithambaram Shaalini. |
| 2009 | Multivoltage multifrequency low-energy synthesis for functionally pipelined datapath | Xing, Xianwu; Jong, Ching Chuen |
| 2001 | Power optimization in data path allocation for high-level synthesis | Zheng, Yuhong. |
| | 2011 | Scalable linear array architectures for matrix inversion using Bi-z CORDIC | Luo, J. W.; Jong, Ching Chuen |
