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| Issue Date | Title | Author(s) |
 | 2019 | A 0.044-mm2 0.5-to-7-GHz resistor-plus-source-follower-feedback noise-cancelling LNA achieving a flat NF of 3.3±0.45 dB | Yu, Haohong; Chen, Yong; Boon, Chirn Chye; Li, Chenyang; Mak, Pui-In; Martins, Rui P. |
| 2017 | 0.058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss | Boon, Chirn Chye; Balachandran, Arya; Chen, Yong; Choi, Pilsoon |
| | 2011 | A 0.6-V high reverse-isolation through feedback self-cancellation for single-stage noncascode CMOS LNA | Tran, T. T. N.; Boon, Chirn Chye; Do, Manh Anh; Yeo, Kiat Seng |
| | 2012 | A 1.2 V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver | Boon, Chirn Chye; Krishna, M. Vamshi; Do, Manh Anh; Yeo, Kiat Seng; Do, Aaron V.; Wong, T. S. |
| | 2012 | A 100 GHz transformer-based varactor-less VCO with 11.2% tuning range in 65nm CMOS technology | Yi, Xiang; Boon, Chirn Chye; Lin, Jia Fu; Lim, Wei Meng |
| 2018 | A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique | Liang, Zhipeng; Yi, Xiang; Yang, Kaituo; Boon, Chirn Chye |
| | 2017 | A 20.2–57.1 GHz Inductor-less Divide-by-4 Divider Chain | Yi, Xiang; Liang, Zhipeng; Boon, Chirn Chye |
| 2015 | A 220-285 GHz SPDT Switch in 65-nm CMOS Using Switchable Resonator Concept | Meng, Fanyi; Ma, Kaixue; Yeo, Kiat Seng; Boon, Chirn Chye; Lim, Wei Meng; Xu, Shanshan |
| 2019 | A 24/77 GHz dual-band receiver for automotive radar applications | Yi, Xiang; Feng, Guangyin; Liang, Zhipeng; Wang, Cheng; Liu, Bei; Li, Chenyang; Yang, Kaituo; Boon, Chirn Chye; Xue, Quan |
| 2009 | A 3-8 GHz low-noise CMOS amplifier | Meaamar, Ali; Boon, Chirn Chye; Do, Manh Anh; Yeo, Kiat Seng |
| 2018 | A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications | Sunny, Sharma; Chen, Yong; Boon, Chirn Chye |
| | 2013 | A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS | Yi, Xiang; Boon, Chirn Chye; Liu, Hang; Lin, Jia Fu; Ong, Jian Cheng; Lim, Wei Meng |
| 2009 | Analytical high frequency channel thermal noise modeling in deep sub-micron MOSFETs | Ong, Shih Ni; Yeo, Kiat Seng; Chew, Kok Wai Johnny; Chan, Lye Hock; Loo, Xi Sung; Do, Manh Anh; Boon, Chirn Chye |
| 2008 | An area efficient high turn ratio monolithic transformer for silicon RFIC | Lim, Chee Chong; Yeo, Kiat Seng; Chew, Kok Wai Johnny; Lim, Suh Fei; Boon, Chirn Chye; Qiu, Ping; Do, Manh Anh; Chan, Lap |
| 2014 | Cell-based variable-gain amplifiers with accurate dB-linear characteristic in 0.18 µm CMOS technology | Liu, Hang; Zhu, Xi; Boon, Chirn Chye |
| | 2013 | A compact coupling controllable elliptical filter based on multilayer LTCC | Meng, Fanyi; Ma, Kaixue; Yeo, Kiat Seng; Boon, Chirn Chye; Xu, Shanshan; Lim, Wei Meng; Do, Manh Anh |
| 2015 | Design and analysis of a K-band wideband voltage-controlled oscillator with robust start-up and frequency boost | Sun, Junyi; Boon, Chirn Chye; Yi, Xiang; Lim, Wei Meng; Meng, Fanyi |
| 2010 | Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler | Yeo, Kiat Seng; Boon, Chirn Chye; Lim, Wei Meng; Do, Manh Anh; Krishna, Manthena Vamshi |
| 2010 | Design of a CMOS broadband transimpedance amplifier with active feedback | Lu, Zhenghao; Yeo, Kiat Seng; Lim, Wei Meng; Do, Manh Anh; Boon, Chirn Chye |
| 2011 | Design of a hysteresis frequency lock detector for dual-loops clock and data recovery circuit | Tan, Yung Sern; Yeo, Kiat Seng; Boon, Chirn Chye; Do, Manh Anh |
