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| Issue Date | Title | Author(s) |
| | 2017 | A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS | Balachandran, Arya; Chen, Yong; Boon, Chirn Chye |
 | 2019 | A 0.044-mm2 0.5-to-7-GHz resistor-plus-source-follower-feedback noise-cancelling LNA achieving a flat NF of 3.3±0.45 dB | Yu, Haohong; Chen, Yong; Boon, Chirn Chye; Li, Chenyang; Mak, Pui-In; Martins, Rui P. |
| 2017 | 0.058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss | Boon, Chirn Chye; Balachandran, Arya; Chen, Yong; Choi, Pilsoon |
| | 2011 | A 0.6-V high reverse-isolation through feedback self-cancellation for single-stage noncascode CMOS LNA | Tran, T. T. N.; Boon, Chirn Chye; Do, Manh Anh; Yeo, Kiat Seng |
| | 2012 | A 1.2 V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver | Boon, Chirn Chye; Krishna, M. Vamshi; Do, Manh Anh; Yeo, Kiat Seng; Do, Aaron V.; Wong, T. S. |
| | 2012 | A 100 GHz transformer-based varactor-less VCO with 11.2% tuning range in 65nm CMOS technology | Yi, Xiang; Boon, Chirn Chye; Lin, Jia Fu; Lim, Wei Meng |
| 2018 | A 2.6–3.4 ghz fractional-N sub-sampling phase-locked loop using a calibration-free phase-switching-sub-sampling technique | Liang, Zhipeng; Yi, Xiang; Yang, Kaituo; Boon, Chirn Chye |
| | 2017 | A 20.2–57.1 GHz Inductor-less Divide-by-4 Divider Chain | Yi, Xiang; Liang, Zhipeng; Boon, Chirn Chye |
| 2015 | A 220-285 GHz SPDT Switch in 65-nm CMOS Using Switchable Resonator Concept | Meng, Fanyi; Ma, Kaixue; Yeo, Kiat Seng; Boon, Chirn Chye; Lim, Wei Meng; Xu, Shanshan |
| 2019 | A 24/77 GHz dual-band receiver for automotive radar applications | Yi, Xiang; Feng, Guangyin; Liang, Zhipeng; Wang, Cheng; Liu, Bei; Li, Chenyang; Yang, Kaituo; Boon, Chirn Chye; Xue, Quan |
| 2009 | A 3-8 GHz low-noise CMOS amplifier | Meaamar, Ali; Boon, Chirn Chye; Do, Manh Anh; Yeo, Kiat Seng |
| 2020 | A 311.6 GHz phase-locked loop in 0.13 μm SiGe BiCMOS process with –90 dBc/Hz in-band phase noise | Liang, Yuan; Boon, Chirn Chye; Chen, Qian; Liu, Zhe; Li, Chenyang; Mausolf, Thomas; Kissinger, Dietmar; Wang, Yong; Ng, Herman Jalli |
| 2020 | A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter | Chen, Qian; Liang, Yuan; Kim, Bongjin; Boon, Chirn Chye |
| 2018 | A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications | Sunny, Sharma; Chen, Yong; Boon, Chirn Chye |
| | 2018 | A 40 GHz on-chip power combine load for mm-wave power amplifier | Lin, Jiafu; Zhang, Gary; Boon, Chirn Chye |
| 2018 | A 52–57 GHz 6-bit phase shifter with hybrid of passive and active structures | Quan, Xing; Yi, Xiang; Boon, Chirn Chye; Yang, Kaituo; Li, Chenyang; Liu, Bei; Liang, Zhipeng; Zhuang, Yiqi |
| | 2013 | A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS | Yi, Xiang; Boon, Chirn Chye; Liu, Hang; Lin, Jia Fu; Ong, Jian Cheng; Lim, Wei Meng |
| 2016 | A 65nm CMOS carrier-aggregation transceiver for IEEE 802.11 WLAN applications | Yi, Xiang; Yang, Kaituo; Liang, Zhipeng; Liu, Bei; Devrishi, Khanna; Boon, Chirn Chye; Li, Chenyang; Feng, Guangyin; Regev, Dror; Shilo, Shimi; Meng, Fanyi; Liu, Hang; Sun, Junyi; Hu, Gengen; Miao, Yannan |
| 2020 | A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS | Chen, Qian; Liang, Yuan; Boon, Chirn Chye |
| 2019 | A 93.4–104.8-GHz 57-mW fractional- N cascaded PLL with true in-phase injection-coupled QVCO in 65-nm CMOS technology | Yi, Xiang; Liang, Zhipeng; Feng, Guangyin; Meng, Fanyi; Wang, Cheng; Li, Chenyang; Yang, Kaituo; Liu, Bei; Boon, Chirn Chye |
