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| Issue Date | Title | Author(s) |
 | 2021 | A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS | Jo, Yong-Jun; Kim, Ju Eon; Baek, Kwang-Hyun; Kim, Tony Tae-Hyoung |
| | 2017 | A 0.016 mV/mA cross-regulation 5-output SIMO dc-dc buck converter using output-voltage-aware charge control scheme | Pham, Ngoc-Son; Yoo, Taegeun; Kim, Tony Tae-Hyoung; Lee, Chan-Gun; Baek, Kwang-Hyun |
| 2016 | 0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization | Do, Anh Tuan; Lee, Zhao Chuan; Wang, Bo; Chang, Ik-Joon; Liu, Xin; Kim, Tony Tae-Hyoung |
| 2008 | A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing | Kim, Tony Tae-Hyoung; Liu, Jason.; Keane, John.; Kim, Chris H. |
| 2017 | A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance | Wang, Bo; Zhou, Jun; Kim, Tony Tae-Hyoung |
| | 2018 | A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS | Le, Van Loi; Li, Juhui; Chang, Alan; Kim, Tony Tae-Hyoung |
| | 2013 | A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches | Kim, Tony Tae-Hyoung; Yeoh, Yuan Lin; Wang, Bo; Yu, Xiangyao |
| 2020 | A 0.5 V 8-12 bit 300 KSPS SAR ADC with adaptive conversion time detection-and-control for high immunity to PVT variations | Kim, Ju Eon; Yoo, Taegeun; Jung, Dong-Kyu; Yoon, Dong-Hyun; Seong, Kiho; Kim, Tony Tae-Hyoung; Baek, Kwang-Hyun |
| 2014 | 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance | Do, Anh Tuan; Yin, Chun; Velayudhan, Kavitha; Lee, Zhao Chuan; Yeo, Kiat Seng; Kim, Tony Tae-Hyoung |
| 2003 | A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM | Cho, Uk Rae; Kim, Tony Tae-Hyoung; Yoon, Yong-Jin; Lee, Jong Cheol; Bae, Dae Gi; Kim, Nam Seog; Kim, Kang Young; Son, Young Jae; Yang, Jeong Suk; Sohn, Kwon Il; Kim, Sung Tae; Lee, In Yeol; Lee, Kwang Jin; Kang, Tae Gyoung; Kim, Su Chul; Ahn, Kee Sik; Byun, Hyun Geun |
| 2019 | A 256 pixel, 21.6 μW infrared gesture recognition processor for smart devices | Ba, Ngoc Le; Oh, Sechang; Sylvester, Dennis; Kim, Tony Tae-Hyoung |
| 2018 | A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation | Kim, Tony Tae-Hyoung; Lee, Zhao Chuan; Do, Anh Tuan |
| 2014 | A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring | Liu, Xin; Zhou, Jun; Yang, Yongkui; Wang, Bo; Lan, Jingjing; Wang, Chao; Luo, Jianwen; Goh, Wang Ling; Kim, Tony Tae-Hyoung; Je, Minkyu |
| | 2012 | A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement | Li, Qi; Wang, Bo; Kim, Tony Tae-Hyoung |
| | 2022 | A 65-nm 8T SRAM compute-in-memory macro with column ADCs for processing neural networks | Yu, Chengshuo; Yoo, Taegeun; Chai, Kevin Tshun Chuan; Kim, Tony Tae-Hyoung; Kim, Bongjin |
| | 2018 | An 88% efficiency 0.1–300-μW energy harvesting system with 3-D MPPT using switch width modulation for IoT smart nodes | Rawy, Karim; Yoo, Taegeun; Kim, Tony Tae-Hyoung |
| 2018 | An area and energy efficient ultra-low voltage level shifter with pass transistor and reduced-swing output buffer in 65-nm CMOS | Le, Van Loi; Kim, Tony Tae-Hyoung |
| 2018 | An area efficient 1024-point low power radix-22 FFT processor with feed-forward multiple delay commutators | Le Ba, Ngoc; Kim, Tony Tae-Hyoung |
| | 2018 | An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS | Do, Anh Tuan; Seyed Mohammad Ali Zeinolabedin; Jeon, Dongsuk; Sylvester, Dennis; Kim, Tony Tae-Hyoung |
| 2016 | Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM | Ho, Weng-Geng; Ne, Kyaw Zwa Lwin; Prashanth Srinivas, Nagarajan; Chong, Kwen-Siong; Kim, Tony Tae-Hyoung; Gwee, Bah Hwee |
