| Issue Date | Title | Author(s) |
| | 2021 | A 0.061-mm² 1–11-GHz noise-canceling low-noise amplifier employing active feedforward with simultaneous current and noise reduction | Liu, Zhe; Boon, Chirn Chye; Yu, Xiaopeng; Li, Chenyang; Yang, Kaituo; Liang, Yuan |
 | 2021 | A 13.5-Gb/s 140-GHz silicon redriver exploiting metadevices for short-range OOK communications | Liang, Yuan; Boon, Chirn Chye; Zhang, Haochi; Tang, Xiao-Lan; Zhang, Qingfeng; Yu, Hao |
| | 2022 | A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector | Liang, Yuan; Boon, Chirn Chye; Chen, Qian |
| 2020 | A 311.6 GHz phase-locked loop in 0.13 μm SiGe BiCMOS process with –90 dBc/Hz in-band phase noise | Liang, Yuan; Boon, Chirn Chye; Chen, Qian; Liu, Zhe; Li, Chenyang; Mausolf, Thomas; Kissinger, Dietmar; Wang, Yong; Ng, Herman Jalli |
| 2020 | A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter | Chen, Qian; Liang, Yuan; Kim, Bongjin; Boon, Chirn Chye |
| 2022 | A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector | Liang, Yuan; Boon, Chirn Chye |
| 2020 | A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS | Chen, Qian; Liang, Yuan; Boon, Chirn Chye |
| 2018 | A crosstalk-immune sub-THz All-surface-wave I/O transceiver in 65-nm CMOS | Liang, Yuan; Boon, Chirn Chye; Yu, Hao |
| 2018 | D-band surface-wave modulator and signal source with 40 dB extinction ratio and 3.7 mW output power in 65 nm CMOS | Liang, Yuan; Yu, Hao; Boon, Chirn Chye; Li, Chenyang; Kissinger, Dietmar; Wang, Yong |
| 2019 | Design and analysis of D-Band on-chip modulator and signal source based on split-ring resonator | Liang, Yuan; Boon, Chirn Chye; Li, Chenyang; Tang, Xiao-Lan; Ng, Herman Jalli; Kissinger, Dietmar; Wang, Yong; Zhang, Qingfeng; Yu, Hao |
| 2022 | A low-jitter and low-reference-spur 320 GHz signal source with an 80 GHz integer-N phase-locked loop using a quadrature XOR technique | Liang, Yuan; Boon, Chirn Chye; Qi, Gengzhen; Dziallas, Giannino; Kissinger, Dietmar; Ng, Herman Jalli; Mak, Pui-In; Wang, Yong |
| 2021 | A low-power quadrature LO generator with mutual power-supply rejection technique | Zhou, Ao; Ding, Xin; Boon, Chirn Chye; Siek, Liter; Liang, Yuan; Dong ,Yangtao |
| 2020 | Multi-channel FSK inter/intra-chip communication by exploiting field-confined slow-wave transmission line | Chen, Qian; Boon, Chirn Chye; Zhang, Xueyong; Li, Chenyang; Liang, Yuan; Liu, Zhe; Guo, Ting |
| 2015 | On-chip sub-terahertz surface plasmon polariton transmission lines in CMOS | Liang, Yuan; Yu, Hao; Zhang, Hao Chi; Yang, Chang; Cui, Tie Jun |
| 2016 | On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS | Liang, Yuan; Yu, Hao; Wen, Jincai; Anak Agung Alit Apriyana; Li, Nan; Luo, Yu; Sun, Lingling |
| 2022 | Siliconization of millimeter-wave to terahertz surface-plasmonic transceiver and phase-locked loops | Liang, Yuan |
