Browsing by Research Centre for Integrated Circuits and Systems

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Issue DateTitleAuthor(s)
2021A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOSJo, Yong-Jun; Kim, Ju Eon; Baek, Kwang-Hyun; Kim, Tony Tae-Hyoung
2020A 1036-F2/bit high reliability temperature compensated cross-coupled comparator-based PUFZhao, Qiang; Wu, Yiheng; Zhao, Xiaojin; Cao, Yuan; Chang, Chip-Hong
2010A 12-bit ultra-low power analog to digital converter design for an infrared imaging systemLiu, Shao Tao.
2020A 311.6 GHz phase-locked loop in 0.13 μm SiGe BiCMOS process with –90 dBc/Hz in-band phase noiseLiang, Yuan; Boon, Chirn Chye; Chen, Qian; Liu, Zhe; Li, Chenyang; Mausolf, Thomas; Kissinger, Dietmar; Wang, Yong; Ng, Herman Jalli
201460GHz low noise amplifierNeo, Kah Wei
2016A 65nm CMOS operational amplifier for analog/mixed-signal circuit applicationsZhang, Yufei
2023AcceleNetor: FPGA-accelerated neural network implementation for side-channel analysisWang, Di 
2020Accelerating homomorphic encryption for privacy-preserving applicationsHo, Truong Phu Truan
2016An adaptive pulse-width modulation scheme for DC-AC converters in electric vehiclesTan, Raymond Kang Zhi
2022Addressing the security concerns of IoT : physical unclonable functions with improved reconfigurability, reliability and machine learning attack resistanceShah, Nimesh Kirit
2009Analog smart I/O padsTan, Shyue Mei.
2011Analysis and design of a CMOS sample-and-hold circuit for biomedical applicationsShiv Kumar Mishra.
2010Analysis and design of a digital class D power amplifierGan, Hoe Yee
2015Analysis and design of a highly efficient and versatile DC-DC converterYu, Guolei
2009Analysis and design of high speed low power 4-bit ALUHuang, Si Wei.
2019Analysis of circuit aging on accuracy degradation of deep neural network acceleratorLiu, Wenye; Chang, Chip-Hong
2009Analytical high frequency channel thermal noise modeling in deep sub-micron MOSFETsOng, Shih Ni; Yeo, Kiat Seng; Chew, Kok Wai Johnny; Chan, Lye Hock; Loo, Xi Sung; Do, Manh Anh; Boon, Chirn Chye
2018Arbiter PUF based FPGA chip identification and authentication methods with enhanced reliability and modeling attack resistanceZalivaka, Siarhei S.
2016Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAMHo, Weng-Geng; Ne, Kyaw Zwa Lwin; Prashanth Srinivas, Nagarajan; Chong, Kwen-Siong; Kim, Tony Tae-Hyoung; Gwee, Bah Hwee
2009Asynchronous circuit compiler designTan, Lik Sin.