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| Issue Date | Title | Author(s) |
| | 2017 | A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS | Balachandran, Arya; Chen, Yong; Boon, Chirn Chye |
| | 2017 | A 0.016 mV/mA cross-regulation 5-output SIMO dc-dc buck converter using output-voltage-aware charge control scheme | Pham, Ngoc-Son; Yoo, Taegeun; Kim, Tony Tae-Hyoung; Lee, Chan-Gun; Baek, Kwang-Hyun |
 | 2019 | A 0.044-mm2 0.5-to-7-GHz resistor-plus-source-follower-feedback noise-cancelling LNA achieving a flat NF of 3.3±0.45 dB | Yu, Haohong; Chen, Yong; Boon, Chirn Chye; Li, Chenyang; Mak, Pui-In; Martins, Rui P. |
| 2017 | 0.058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss | Boon, Chirn Chye; Balachandran, Arya; Chen, Yong; Choi, Pilsoon |
| 2017 | A 0.058 mm2 24 µw temperature sensor in 40 nm cmos process with ± 0.5 ◦c inaccuracy from −55 to 175 ◦c | Zhu, Di; Siek, Liter |
| 2004 | 0.18-µm CMOS push-pull power amplifier with antenna in IC package | Wang, Wei; Zhang, Yue Ping |
| 2018 | A 0.18-μm CMOS voltage-to-frequency converter with low circuit sensitivity | Koay, Kuan Chuang; Chan, Pak Kwong |
| 2008 | A 0.18μm CMOS 802.15.4a UWB transceiver for communication and localization | Zheng, Yuanjin; Arasu, Muthukumaraswamy Annamalai; Wong, King Wah; The, Yen Ju; Poh, Andrew Hoe Suan; Tran, Duy Duong; Yeoh, Wooi Gan; Kwong, Dim Lee |
| | 2012 | A 0.18μm front end for ECG/EEG/neural sensor interface | Han, Dong; Zheng, Yuanjin; Je, Minkyu |
| 2016 | 0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization | Do, Anh Tuan; Lee, Zhao Chuan; Wang, Bo; Chang, Ik-Joon; Liu, Xin; Kim, Tony Tae-Hyoung |
| 2008 | A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing | Kim, Tony Tae-Hyoung; Liu, Jason.; Keane, John.; Kim, Chris H. |
| | 2018 | 0.2 λ0 thick adaptive retroreflector made of spin-locked metasurface | Yan, Libin; Zhu, Weiming; Muhammad Faeyz Karim; Cai, Hong; Gu, Alex Yuandong; Shen, Zhongxiang; Chong, Peter Han Joo; Kwong, Dim-Lee; Qiu, Cheng-Wei; Liu, Ai Qun |
| 2017 | A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance | Wang, Bo; Zhou, Jun; Kim, Tony Tae-Hyoung |
| | 2013 | A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS | Han, Dong; Zheng, Yuanjin; Rajkumar, Ramamoorthy; Dawe, Gavin; Je, Minkyu |
| | 2013 | A 0.4V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches | Kim, Tony Tae-Hyoung; Yeoh, Yuan Lin; Wang, Bo; Yu, Xiangyao |
| | 2011 | A 0.6-V high reverse-isolation through feedback self-cancellation for single-stage noncascode CMOS LNA | Tran, T. T. N.; Boon, Chirn Chye; Do, Manh Anh; Yeo, Kiat Seng |
| | 2013 | 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique | Yu, Xiao Peng; Lu, Zhenghao; Lim, Wei Meng; Yeo, Kiat Seng |
| 2014 | 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance | Do, Anh Tuan; Yin, Chun; Velayudhan, Kavitha; Lee, Zhao Chuan; Yeo, Kiat Seng; Kim, Tony Tae-Hyoung |
| | 2011 | A 0.8-μW window SAR ADC with offset cancellation for digital DC–DC converters | Foong, Huey Chian; Tan, Meng Tong; Zheng, Yuanjin |
| | 2013 | A 0.9-µ A quiescent current output-capacitorless LDO regulator with adaptive power transistors in 65-nm CMOS | Chong, Sau Siong; Chan, Pak Kwong |
