Academic Profile : Faculty

Prof Gan Chee Lip.jpg picture
Prof Gan Chee Lip
Associate Provost (Undergraduate Education)
Professor, School of Materials Science & Engineering
Director, CSA-NTU Joint Center (CNJC)
Executive Director, Office of Research and Technology in Defence and Security (ORTDS)
 
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Dr Gan is a Professor at the School of Materials Science and Engineering (MSE), Nanyang Technological University. He is currently the Associate Provost (Undergraduate Education) and Executive Director of Office of Research & Technology in Defence & Security (ORTDS). He is also a Fellow of Renaissance Engineering Programme (REP), as well as a Fellow of NTU Teaching Excellence Academy. He had previously held the position of Assistant Chair of Alumni and Head of Materials Science Division in School of MSE, Chairman of NTU Teaching Council, Director of REP, Director of Temasek Laboratories@NTU and Deputy Associate Provost (Undergraduate Education). Dr Gan was awarded the National Day Award Bronze Medal (Administration) in 2013, the Nanyang Education Award (University, Gold) in 2015, the Defence Technology Prize (Team R&D) in 2016, and the Defence Technology Prize (Individual R&D) in 2018.

Dr Gan received his B.Eng (Electrical) from the National University of Singapore in 1999, and Ph.D in Advanced Materials for Micro- and Nano-Systems under the Singapore-MIT Alliance Program (SMA) in 2003. His research interests include the reliability study of GaN-on-Si devices, failure analysis of microelectronics devices, development of advanced packaging materials and technology for harsh environment electronics, and development of ceramic pastes for 3D printing. He has received a number of best paper and poster awards at international conferences, as well as being an invited, keynote and plenary speaker at these conferences. His research on using copper nanostructures for low temperature bonding in electronics packaging and other applications has led to the spin-off of a NTU start-up company, Kuprion Inc. in 2016.

Outside of NTU, Dr Gan is a Senior Member of IEEE and past Chairman of IEEE Singapore Reliability/ED/CPMT joint chapter. He is also currently the Chairman of the International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Board.
• Hardware (i.e. electronics/microelectronics) assurance and security
• Microelectronics failure analysis and reliability (e.g. interconnects, III-V devices, electronic packages)
• Packaging technology for harsh environment electronics (e.g. copper nanoparticles bonding, high temperature encapsulant)
• 3D printing of ceramics (e.g. alumina, zirconia, transparent ceramics)
 
  • [NRF/NCR/CFACore] Cyber Forensics & Assurance Core R&D Programme
  • [NRF/NCR/CFAMgt] Cyber Forensics & Assurance Project Management
  • Application Development Of NanoCu Technology
  • Cyber Security Agency (CSA) Funding to NTU for National Integrated Centre for Evaluation (NICE)
  • Hardware Assurance Phase II
  • Hardware Security Thrust (i): Development of non-invasive and invasive techniques for the evaluation and vulnerability analysis of hardware security mechanisms in target device up to chip level
  • Hardware Security: Research and Development on Hardware Vulnerability Analysis
  • LEES+ Monolithic CMOS + GaN HEMT Integrated Circuits for 5G and Beyond
  • Pressureless, Ultrafast Sintering of Advanced Ceramics with Complex Shapes
  • Project ACOA- 3D Printing of Advanced Ceramics with High Thermal Conductivity and Light-weighting Design for Telescope Application
  • PROJECT CARMICS
  • Research and Development of Advanced Imaging Techniques for Semiconductor Devices
  • Sample Preparation Methodologies for Advanced Semiconductor Devices
  • The Management and Maintenance of the Microelectronics Failure Analysis Lab Goco Facility
  • WP3 Reliability Study & Failure Analysis of Monolithic CMOS + GaN HEMT ICs
US 2018/0237644 A1: Conductive Paste, Method For Forming An Interconnection And Electrical Device (2019)
Abstract: According to embodiments of the present invention, a conductive paste is provided. The conductive paste has a composition including a plurality of conductive nanoparticles and a plurality of conductive nanowires, wherein a weight ratio of the plurality of conductive nanoparticles to the plurality of conductive nanowires is between about 10:1 and about 50:1. According to further embodiments of the present invention, a method for forming an interconnection and an electrical device are also provided.

US 2018/0002540 A1: Conductive Paste, Method For Forming An Interconnection And Electrical Device (2018)
Abstract: According to embodiments of the present invention, a conductive paste is provided. The conductive paste has a cam-position including a plurality of conductive nanoparticles and a plurality of conductive nanowires, wherein a weight ratio of the plurality of conductive nanoparticles to the plurality of conductive nanowires is between about 10:1 and about 50:1. According to further embodiments of the present invention, a method for forming an interconnection and an electrical device are also provided.