Academic Profile : Faculty

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Prof Zhang Yue Ping
Professor, School of Electrical & Electronic Engineering
Y. P. Zhang received the B. E. and M. E. degrees from Taiyuan Polytechnic Institute and Shanxi Mining Institute of Taiyuan University of Technology, Shanxi, China, in 1982 and 1987, respectively and the PhD. degree from the Chinese University of Hong Kong, Hong Kong, in 1995, all in electronic engineering.

From 1982 to 1984, he worked at Shanxi Electronic Industry Bureau, from 1990 to 1992, the University of Liverpool, Liverpool, U. K., and from 1996 to 1997, City University of Hong Kong. From 1987 to 1990, he taught at Shanxi Mining Institute and from 1997 to 1998, the University of Hong Kong. He was promoted to a Full Professor at Taiyuan University of Technology in 1996. He is now Professor of Electronic engineering with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. He has broad interests in radio science and technology and published widely in the field.

He received the Sino-British Technical Collaboration Award in 1990 for his contribution to the advancement of subsurface radio science and technology. He received the Best Paper Award from the Second IEEE International Symposium on Communication Systems, Networks and Digital Signal Processing, 18-20th July 2000, Bournemouth, UK and the Best Paper Prize from the Third IEEE International Workshop on Antenna Technology, 21-23rd March 2007, Cambridge, UK. He was awarded a William Mong Visiting Fellowship from the University of Hong Kong in 2005. He received the S. A. Schelkunoff Transactions Prize Paper Award in 2012 from the IEEE Antennas and Propagation Society.

He was a Guest Editor of the International Journal of RF and Microwave Computer-Aided Engineering. He serves as an Editor of ETRI Journal, an Associate Editor of the IEEE Transactions on Antennas and Propagation, and an Associate Editor of the International Journal of Electromagnetic Waves and Applications. He also serves on the Editorial Boards of a large number of Journals including the IEEE Transactions on Microwave Theory and Techniques and the IEEE Microwave and Wireless Components Letters.

He is a Fellow of IEEE.
He has broad interests in radio science and technology with current emphasis on MMIC and RFIC design for wireless chip area network and antenna-in-package (AiP) technology for single-chip radio devices.
US 2014/0327495 A1: SPST Switch, SPDT Switch, SPMT Switch And Communication Device Using The Same (2016)
Abstract: Various embodiments provide a single pole single throw switch. The switch may include a first terminal, a second terminal and a control terminal; a field-effect transistor having a drain connected to the first terminal, a source connected to the ground, and a gate; a bias resistor connected between the gate of the field-effect transistor and the control terminal; an inductor connected between the first terminal and the second terminal; and a capacitor having one end connected to the second terminal and another end connected to the ground.

US 2011/0241969 A1: Grid Array Antennas and Integration Structure (2014)
Abstract: A grid array antenna configured to operate with millimetre wavelength signals, the grid array antenna comprising a plurality of mesh elements and at least one radiation element; each mesh element comprising at least one long side and at least one short side operatively connected to the at least one long side; at least one of: the at least one radiating element, the at least one short side, and the at least one long side having compensation for improved antenna output for improved antenna radiation.

US-2010-0001351-A1: Triple Well Transmit-Receive Switch Transistor (2012)
Abstract: A transistor arrangement including a triple well structure, the triple well structure including a substrate of a first conductivity type, a first well region of a second conductivity type formed within the substrate and a second well region of the first conductivity type being separated from the substrate by the first well region. The transistor arrangement further includes a first transistor formed on or in the second well region, the first transistor including a body terminal being connected to the second well region and a second well region switch being connected to the body terminal of the first transistor.