Academic Profile

KT Lau served as program director for two Master of Science programs and is an associate professor at the School of Electrical and Electronic Engineering. He has worked in multinational corporations, in Silicon Valley (California) and elsewhere, where he was involved in the design of CMOS integrated circuits and manufacturing of microelectronics/optoelectronics products. He was at ESIEE Paris on an academic exchange program. KT has published more than 100 papers in international journals and conference proceedings and has served as a reviewer for many international publications, including various IEEE, IEE/IET publications, and other international journals and conferences. KT has also served as an external assessor for a research funding agency and as external examiner for graduate-level theses and dissertations. He teaches courses in electronics and integrated circuit design at the School of Electrical and Electronic Engineering. His current research activities are focused on low power integrated circuits and applications. KT received academic degrees from Cornell University.
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Assoc Prof Lau Kim Teen (No longer with NTU)
Associate Professor, School of Electrical & Electronic Engineering

Ultra Low Power IC Design
Adiabatic CMOS Circuit Design
Self-Timed CMOS Circuit Design
Radiation-hardened CMOS Circuit Design
CMOS Circuits for IoT Applications
  • Irina Alam and KT Lau. (2017). Approximate Adder for Low Power Computations. International Journal of Electronics Letters, 5(2), 158-165.

  • Yang Shaochen, Lau KT and Zhang Yufei. (2016). Design of Low Power CMOS Parallel Prefix Adder Cell. Journal of Electrical Engineering and Electronic Technology, 5(1).

  • Ramakrishnan S and Lau K T. (2008). Improved Dynamic Current Mode Logic for Low Power Applications. Journal of Circuits Systems and Computers, 17(2), 183-190.

  • Ng K W and Lau K T. (2000). A Novel Adiabatic Register File Design. Journal of Circuits Systems and Computers, 10(1-2), 67-76.

  • Liu F and Lau K T. (1998). Pass-Transistor Adiabatic Logic with NMOS Pull-down Configuration. Electronics Letters, 34(8), 739-741.