Academic Profile : Faculty

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Assoc Prof Boon Chirn Chye
Associate Professor, School of Electrical & Electronic Engineering
External Links
 
Chirn Chye Boon (M’09-SM’10) received B.E. (Hons.) (Elect.) in 2000 and Ph.D. (Elect. Eng.) in 2004 from Nanyang Technological University (NTU), Singapore. Since 2005, Chirn Chye has been with NTU where he is currently an Associate Professor. Before that, he was with Advanced RFIC (Singapore), where he worked as a Senior Engineer.
He is the Programme Director for RF and MM-wave research in the S$50million research centre of excellence, VIRTUS (NTU) since March 2010. He is the Principal Investigator for research grants of over S$13 million. He is a key NTU-team members of MIT-NTU joint collaboration project “Low Energy Electronic Systems”, under Singapore-MIT Alliance for Research and Technology (SMART) with a grant total of S$25million. He is also a key member of an Industry Alignment Fund (IAF-PP) on “Next-Generation V2X” with a grant total of S$21million. He is a winner of Year-2 Teaching Excellence Award and Commendation Award for Excellent Teaching Performance, EEE, NTU.
He is an Associate Editor for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the IEEE Electron Devices Letters Golden Reviewer. He specializes in the areas of radio frequency (RF) & MM-wave circuits design for Communications applications. He has conceptualized, designed and silicon-verified many circuits/chips resulting in over 160 refereed publications and over 30 patents in the fields of RF and MM-wave. He is a co-author of the book “Design of CMOS RF Integrated Circuits and Systems” and “CMOS Millimeter-Wave Integrated Circuits for Next Generation Wireless Communication Systems (World Scientific Publishing).


Other Awards:

· FIRST Singapore ISSCC Silkroad Award paper winner (2013). ISSCC is the world TOP IC conference..

• IEEE Electron Devices Letters GOLDEN REVIEWER 2012

• IEEE Senior Member (2010)

• Represents NTU for the Asia Pacific Economic Cooperation SCIENCE PRIZE for INNOVATION, RESEARCH and EDUCATION (ASPIRE)

• Year-2 Teaching Excellent Award, EEE, NTU (2012) : For Lecture of 639 students.

• Best Project of Design Innovation Project Competition, EEE, NTU (2012)
Please See link below for more publications and awards.
https://www3.ntu.edu.sg/home/eccboon/
PI: WP1: Transceiver Development Applicable for Hybrid “C-V2X+DSRC” V2X-System, S$2,889.900, 1 November 2019 to 31 October 2022, A*STAR (STAT Board), SERC A19D6a0053.

PI: Keysight Technologies Singapore – NTU Joint R&D: Transceiver test and development applicable for V2X-System and mmW, S$1,783.750, 22 January 2020 to 21 January 2023, Keysight Technologies Singapore (Industry).

PI: LEES III-V + CMOS Circuits & System towards Commercialization, S$364,800, 1 July 2019 to 31 December 2021, LEES-SMART-IRG (SMART No. II-16 LEES IRG), Phase II.

PI: Industry: Wireless Heterogeneous Network Transceiver Chipset for Content-Driven Transmission of Learning Media (SLE-RP3) Research Area (SLE), 1st July 2016 to 30th June 2021.

PI: Monolithic Terahertz Passive Components in Advanced CMOS Technology: From Fundamental Understandings to Integrated Circuit Applications, 1st November 2016 to 31st October 2018.

PI: Industry: Circuit Design for GaN Based DC-DC Converter Power, 1st June 2016 to 31st December 2018..

Industry: An Integrated Platform Approach Towards Non-Invasive Continuous Blood Glucose Monitoring Addressing Clinical Need for Early Diagnosis and Improved Compliance, 1st July 2016 to 30th July 2018.

PI: Industrial Grant (Fortune 500 Company) 10GiFi research & development of ultra-wideband RF transceiver, S$927,840.00, 15th July 2014 to 14th July 201.

PI: High Thermal Resolution Ultra-Low Power Integrated Imager: Fund. Issues in CMOS, $840,000, July 2013 to June 2016, AcRF Tier 2 MOE.

PI: Project 2: Electronic Circuit Design, Communication, S$391,560, April. 2012 to March 2013, LEES-SMART-IRG.

PI: Project 2: Electronic Circuit Design, Communication, S$376,200, April. 2013 to March 2014, LEES- SMART-IRG. Due to his excellent work and performance, he was again awarded this subcontract.

PI: Project 2: Electronic Circuit Design, Communication, S$836,400, April. 2014 to March 2016, LEES-SMART-IRG.

Recently, due to the outstanding feedback on Jan 2014 LEES Annual Review Meeting, he was further awarded a large subcontract amount of S$836,400 as PI under the “Low Energy Electronic Systems” from April 2014 to March 2016. LEES Annual Review Meeting is attended by all the PIs and Scientific Advisory Board (SAB) members which include Prof. Timothy David Sands who was recently appointed as President of Virginia Tech, USA.

PI: Ultra-low Power Fully Integrated CMOS 24GHz Receiver, $0.323mil, March 2008 to February 2011, AcRF Tier 1 MOE.

PI: Batteryless Flexible Transceiver for Biomedical Applications, $1,186,270 including scholarships), May 2009 to April 2012, AcRF Tier 2 MOE.

Co-PI: An Ultra Low-Power RFIC Chip For Wireless and Communication Applications S$1.2 mil, March 2006 to February 2009, funded by Agency for Science, Technology and Research (A*STAR).

Co-PI: System-on-chip: Realization of Software Radio, S$0.3 mil, 3 December 2008 to 2 December 2009, University of Electronic Science and Technology (UEST) of China-NTU Joint R&D, jointly funded by UEST and NTU.

Co-PI: An Ultra Low-Power RF Transceiver Chip towards a New Paradigm of Life Quality, S$0.25 mil, 3 December 2008 to 2 December 2009, NRF.

Key Collaborator: “Low Energy Electronic Systems” which has won the Singapore-MIT Alliance for Research and Technology (SMART) International Research Grant (IRG) proposal with a grant total of S$25million.

Various JIP programs.
 
  • CMOS Terahertz Plasmonic Interconnect towards Tera-scale Computing
  • High data rate mmWave Techniques for Beyond-5G/6G Smart Drones Communications
  • Next-Generation V2X Network Architecture and Ecosystem for Smart Mobility
  • Transceiver Test and Development Applicable for V2X-System and mmW
US 2020/0168605 Al: High Voltage Logic Circuit (2021)
Abstract: A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed. Also, a logic circuit comprising: a low voltage logic input; a high supply voltage input; a circuit ground voltage input; a high voltage output; a first tail device made from a first semiconductor material; and a second tail device made from a second different semiconductor material; wherein the first and second tail devices are coupled, in series, between the high voltage output and the circuit ground voltage input; and wherein respective gates of the first and second tail devices are coupled, in parallel, to the low voltage logic input.

US 2017/0201268 A1: Analog-To-Digital Converter (2017)
Abstract: An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit.

US 2016/0330795 A1: An Integrated Circuit Adapted for Mobile Communication and Related Mobile Computing Device (2017)
Abstract: An integrated circuit (400) adapted for mobile communication is disclosed. The circuit comprises a first device layer formed of a first semiconductor material and having at least a first circuit portion (402); and a second device layer formed of a second semiconductor material different to the first semiconductor material and having at least a second circuit portion (404), wherein the first and second device layers are integrally formed, and the first circuit portion is electrically coupled to the second circuit portion to enable the mobile communication using first and second wireless communication protocols. A related mobile computing device is also disclosed.

US 2021/0250057 A1: Apparatus And Method For Wireless Communication (2022)
Abstract: An apparatus and method for wireless communication, and a method of fabricating the apparatus. The apparatus comprises two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits; wherein the transceiver array groups are configured to operate at different frequencies; wherein the transceiver array groups are configured to be connected to one corresponding digital baseband processor; and wherein the transceiver array groups comprise at least one first transceiver array group configured to operate at cm wavelength or larger. Preferably, the transceiver array groups comprise at least one second transceiver array group configured to operate at mm wavelength.