Academic Profile : Faculty
Prof Tan Chuan Seng
Associate Dean (Academic), College of Engineering
Professor, School of Electrical & Electronic Engineering
Deputy Chair, School of Electrical and Electronic Engineering (EEE)
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LinkedIn Profile: https://www.linkedin.com/in/chuan-seng-tan-a4b62216
(Updated on Dec 5, 2021) Chuan Seng Tan (FIEEE, FIMAPS) received his B.Eng. degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his M.Eng. degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for 2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon.
He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inaugural Nanyang Assistant Professorship. In March 2014, he was promoted to the rank of Associate Professor (with tenure). In September 2019, he was promoted to the rank of Full Professor. His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology.
He is a Fellow of IEEE (Class of 2022, citation: for contributions to wafer bonding technology for 3D packaging and integration) and a recipient of the Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS) in 2019. Since June 2019, he has been a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019 and a recipient of the William D. Ashman - John A. Wagnon Technical Achievement Award in 2020.
He was the Chair of the Interconnections Sub-Committee for ECTC’2021. He was the General Chair of the 2020 IEEE Electronics Packaging Technology Conference (EPTC). He is currently an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology, and received the Best AE Award in 2021. He is a member of the Technical Working Group of the Heterogeneous Integration Roadmap (HIR) on wafer-level packaging. He serves as an elected Member-at-Large to the IEEE EPS Board of Governors from 2022-2024.
Check out a recent demonstration of a 3D MEMS-CMOS chip (for motion sensing) designed, fabricated and packaged in his group: http://www.youtube.com/watch?v=zpYXEEsE2_E
Check out a project by his students on bicycle phone charger: http://youtu.be/KQptIDgOaGQ
(Updated on Dec 5, 2021) Chuan Seng Tan (FIEEE, FIMAPS) received his B.Eng. degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his M.Eng. degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for 2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon.
He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inaugural Nanyang Assistant Professorship. In March 2014, he was promoted to the rank of Associate Professor (with tenure). In September 2019, he was promoted to the rank of Full Professor. His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology.
He is a Fellow of IEEE (Class of 2022, citation: for contributions to wafer bonding technology for 3D packaging and integration) and a recipient of the Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS) in 2019. Since June 2019, he has been a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019 and a recipient of the William D. Ashman - John A. Wagnon Technical Achievement Award in 2020.
He was the Chair of the Interconnections Sub-Committee for ECTC’2021. He was the General Chair of the 2020 IEEE Electronics Packaging Technology Conference (EPTC). He is currently an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology, and received the Best AE Award in 2021. He is a member of the Technical Working Group of the Heterogeneous Integration Roadmap (HIR) on wafer-level packaging. He serves as an elected Member-at-Large to the IEEE EPS Board of Governors from 2022-2024.
Check out a recent demonstration of a 3D MEMS-CMOS chip (for motion sensing) designed, fabricated and packaged in his group: http://www.youtube.com/watch?v=zpYXEEsE2_E
Check out a project by his students on bicycle phone charger: http://youtu.be/KQptIDgOaGQ
3D packaging and integration, Group-IV hetero-epitaxy (Si, Ge, Sn) and devices
(Updated: Dec 5, 2021) If you are interested in post-doc positions (group-IV Ge/Sn for SWIR photo-detector), please contact tancs@ntu.edu.sg
(Updated: Dec 5, 2021) If you are interested in post-doc positions (group-IV Ge/Sn for SWIR photo-detector), please contact tancs@ntu.edu.sg
- Artificial Low-Dimensional Germanium Nanolaser Enabled by On-Demand Quantum Strain Engineering
- Atomic Layer Process of Semiconductor
- CMOS-Compatible Resonant-Cavity-Enhanced GeSn Single-Photon Avalanche Photodiode – Material, Design and Device
- Development of Wafer Scale Abrupt Semiconductor Hetero-junctions with Defect-free Interfaces for Next Generation Electronic and Photonic Applications
- Hybrid Ion-Traps for Quantum Computing: Embedded-Glass Ion-Trap on Si Interposer for Large Scale Integration (HIT)
- Nanosystems at the Edge
- Novel Tensile Strained GeSn-on-Insulator Platform and High-Performance GeSn Photodetectors for Mid-Infrared Detection
- Study of Copper Wire Bond Reliability Under Biased Humidity Stress Tests (Schedule 1); Copper Corrosion & Life-time Prediction in Humid Condition in Molded Package (Schedule 2)
US 2018/0269276 A1: Semiconductor Device Having A Capacitor And A Through-Substrate Via Conductor (2021)
Abstract: A semiconductor device 100 comprising a substrate 102 having a through-substrate via hole 106, the through-substrate via hole 106 having formed therein: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116. A method of forming a semiconductor device 100, the semiconductor device 100 comprising a through-substrate via hole 106, the method comprising forming, in the through-substrate via hole 106: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116.
US 2019/0051516 A1: Fabrication Of A Device On A Carrier Substrate (2020)
Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.
US 2019/0033523 A1: Optical Structure And Method Of Forming The Same (2020)
Abstract: Various embodiments may provide an optical structure. The optical structure may include a substrate. The optical structure may also include a core layer configured to carry optical light. The core layer may include germanium. The optical structure may further include an intermediate layer separating the substrate and the core layer so that the substrate is isolated from the core layer. The intermediate layer may include one or more materials selected from a group consisting of III-V materials, dielectric materials, and chalcogenide materials. A width of the core layer may be smaller than a width of the intermediate layer. A refractive index of the core layer may be more than 4. A refractive index of the intermediate layer may be smaller than 3.6.
US 2017/0271201 A1: Method of Manufacturing Germanium-on-Insulator Substrate
(2018)
Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.
Abstract: A semiconductor device 100 comprising a substrate 102 having a through-substrate via hole 106, the through-substrate via hole 106 having formed therein: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116. A method of forming a semiconductor device 100, the semiconductor device 100 comprising a through-substrate via hole 106, the method comprising forming, in the through-substrate via hole 106: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116.
US 2019/0051516 A1: Fabrication Of A Device On A Carrier Substrate (2020)
Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.
US 2019/0033523 A1: Optical Structure And Method Of Forming The Same (2020)
Abstract: Various embodiments may provide an optical structure. The optical structure may include a substrate. The optical structure may also include a core layer configured to carry optical light. The core layer may include germanium. The optical structure may further include an intermediate layer separating the substrate and the core layer so that the substrate is isolated from the core layer. The intermediate layer may include one or more materials selected from a group consisting of III-V materials, dielectric materials, and chalcogenide materials. A width of the core layer may be smaller than a width of the intermediate layer. A refractive index of the core layer may be more than 4. A refractive index of the intermediate layer may be smaller than 3.6.
US 2017/0271201 A1: Method of Manufacturing Germanium-on-Insulator Substrate
(2018)
Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.
Courses Taught
EE2003 - SEMICONDUCTOR FUNDAMENTAL