Academic Profile : Faculty
Prof Tan Chuan Seng
Co-Director, National Centre for Advanced Integrated Photonics (NCAIP), School of Electrical & Electronic Engineering
Professor, School of Electrical & Electronic Engineering
Co-Director, National Centre for Advanced Integrated Photonics (NCAIP)
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Chuan Seng Tan is a Professor of Electronic Engineering at the School of Electrical and Electronic Engineering at Nanyang Technological University, Singapore. He received his PhD from MIT in 2006. Currently, he is working on process technology of three-dimensional integrated circuits (3D IC), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and intellectual property on 3D technology and engineered substrates. Some of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology.
He is a Fellow of IEEE and a recipient of the Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS) in 2019. Beginning June 2019, he is a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) and a recipient of the William D. Ashman - John A. Wagnon Technical Achievement Award in 2020.
He was the General Chair of the 2020 IEEE Electronics Packaging Technology Conference (EPTC-Virtual). In addition, he is an Associate Editor for the IEEE Transactions on Components, Packaging and Manufacturing Technology and was recognized with the Best Associate Editor Award in 2021. He serves as an elected Member-at-Large to the IEEE EPS Board of Governors from 2022-2024.
He is a Fellow of IEEE and a recipient of the Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS) in 2019. Beginning June 2019, he is a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) and a recipient of the William D. Ashman - John A. Wagnon Technical Achievement Award in 2020.
He was the General Chair of the 2020 IEEE Electronics Packaging Technology Conference (EPTC-Virtual). In addition, he is an Associate Editor for the IEEE Transactions on Components, Packaging and Manufacturing Technology and was recognized with the Best Associate Editor Award in 2021. He serves as an elected Member-at-Large to the IEEE EPS Board of Governors from 2022-2024.
3D packaging and integration, Group-IV hetero-epitaxy (Si, Ge, Sn) and devices
(Updated: March 2024) If you are interested in post-doc positions (group-IV Ge/Sn for SWIR photo-detector), please contact tancs@ntu.edu.sg
(Updated: March 2024) If you are interested in post-doc positions (group-IV Ge/Sn for SWIR photo-detector), please contact tancs@ntu.edu.sg
- AM2.1: Advanced Coatings for Semiconductor Applications (IAF-ICP) - 01/11/2023 to 31/10/2027
- AM2.2: Advanced Coatings for Semiconductor Applications (IAF-ICP) - 01/11/2023 to 31/10/2027
- Atomic layer etching in advanced nodes semiconductor manufacturing
- Atomic Layer Process of Semiconductor
- Epoxy Mold Compounds for High Voltage Applications
- Ge/GeSn nanomembrane photodetectors
- Germanium-based Single Photon Avalanche Photodiode
- Holistic Analysis of Signal Integrity and Power Integrity for CoWoS Technology Assisted by AI
- Machine-Learning Assisted Integrated Photonics Design and Fabrication for Trapped Ion Addressing
- Monetary Academic Resources
- National Semiconductor Translation and Innovation Centre (NSTIC) – Project (P7) - Demonstrate GaAs gain block integration in SiN (>13 dB gain)
- Selective Dielectric Capping Method for Hybrid Bonding Strength Improvement
- Study of Copper Wire Bond Reliability Under Biased Humidity Stress Tests (Schedule 1); Copper Corrosion & Life-time Prediction in Humid Condition in Molded Package (Schedule 2)
- WP4.1 Advanced Silicon Photonics Platforms
US 2018/0269276 A1: Semiconductor Device Having A Capacitor And A Through-Substrate Via Conductor (2021)
Abstract: A semiconductor device 100 comprising a substrate 102 having a through-substrate via hole 106, the through-substrate via hole 106 having formed therein: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116. A method of forming a semiconductor device 100, the semiconductor device 100 comprising a through-substrate via hole 106, the method comprising forming, in the through-substrate via hole 106: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116.
US 2019/0051516 A1: Fabrication Of A Device On A Carrier Substrate (2020)
Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.
US 2019/0033523 A1: Optical Structure And Method Of Forming The Same (2020)
Abstract: Various embodiments may provide an optical structure. The optical structure may include a substrate. The optical structure may also include a core layer configured to carry optical light. The core layer may include germanium. The optical structure may further include an intermediate layer separating the substrate and the core layer so that the substrate is isolated from the core layer. The intermediate layer may include one or more materials selected from a group consisting of III-V materials, dielectric materials, and chalcogenide materials. A width of the core layer may be smaller than a width of the intermediate layer. A refractive index of the core layer may be more than 4. A refractive index of the intermediate layer may be smaller than 3.6.
US 2017/0271201 A1: Method of Manufacturing Germanium-on-Insulator Substrate
(2018)
Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.
US 2020/0388501 A1: Method of Reducing Semiconductor Substrate Surface Unevenness
(2024)
Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.
Abstract: A semiconductor device 100 comprising a substrate 102 having a through-substrate via hole 106, the through-substrate via hole 106 having formed therein: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116. A method of forming a semiconductor device 100, the semiconductor device 100 comprising a through-substrate via hole 106, the method comprising forming, in the through-substrate via hole 106: a first capacitor electrode layer 108a and a second capacitor electrode layer 108b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 108a and the second capacitor electrode layer 108b; and a through-substrate via conductor 116.
US 2019/0051516 A1: Fabrication Of A Device On A Carrier Substrate (2020)
Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.
US 2019/0033523 A1: Optical Structure And Method Of Forming The Same (2020)
Abstract: Various embodiments may provide an optical structure. The optical structure may include a substrate. The optical structure may also include a core layer configured to carry optical light. The core layer may include germanium. The optical structure may further include an intermediate layer separating the substrate and the core layer so that the substrate is isolated from the core layer. The intermediate layer may include one or more materials selected from a group consisting of III-V materials, dielectric materials, and chalcogenide materials. A width of the core layer may be smaller than a width of the intermediate layer. A refractive index of the core layer may be more than 4. A refractive index of the intermediate layer may be smaller than 3.6.
US 2017/0271201 A1: Method of Manufacturing Germanium-on-Insulator Substrate
(2018)
Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding (102) the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing (104) the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing (106) the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.
US 2020/0388501 A1: Method of Reducing Semiconductor Substrate Surface Unevenness
(2024)
Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.
Awards
Exceptional Technical Achievement Award, IEEE Electronics Packaging Society (EPS), 2019.
William D. Ashman - John A. Wagnon Technical Achievement Award, International Microelectronics Assembly and Packaging Society (IMAPS), 2020.
William D. Ashman - John A. Wagnon Technical Achievement Award, International Microelectronics Assembly and Packaging Society (IMAPS), 2020.
Fellowships & Other Recognition
IEEE Fellow
IMAPS Fellow
IMAPS Fellow
Courses Taught
EE2003 - SEMICONDUCTOR FUNDAMENTAL