Academic Profile : Faculty

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Assoc Prof Kim Tae Hyoung
Associate Professor, School of Electrical & Electronic Engineering
Deputy Director, Centre for Integrated Circuits and Systems, School of Electrical and Electronic Engineering (EEE)
 
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Prof. Tony T. Kim received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. He received the Ph.D. degree in electrical and computer engineering from the University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics where he performed research on the design of high-speed SRAM memories, clock generators, and IO interface circuits. In 2007 ~ 2009 summer, he was with IBM T. J. Watson Research Center and Broadcom Corporation where he performed research on isolated NBTI/PBTI measurement circuits and SRAM Mismatch measurement test structure, and battery backed memory design, respectively. In November 2009, he joined Nanyang Technological University where he is currently an associate professor. His current research interests include low power and high performance digital, mixed-mode, and memory circuit design, ultra-low voltage sub-threshold circuit design for energy efficiency, variation and aging tolerant circuits and systems, approximate computing, and circuit techniques for 3D ICs.

He received Best Demo Award at 2016 IEEE APCCAS, International Low Power Design Contest award at 2016 IEEE/ACM ISLPED, a best paper award at 2014 and 2011 ISOCC, 2008 AMD/CICC Student Scholarship Award, 2008 Departmental Research Fellowship from U. of Minnesota, 2008 IEEE DAC/ISSCC Student Design Contest Award, 2008 Samsung Humantec Thesis Award (Bronze Prize), 2005 ETRI Journal Paper of the Year Award, 2001 Samsung Humantec Thesis Award (Honor Prize), and 1999 Samsung Humantec Thesis Award (Silver Prize). He is an author/co-author of around 120 journal and conference papers and holds 17 US and Korean patents. He serves as an Associate Editor of IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Access, and IEIE Journal of Semiconductor Technology and Science (JSTS). He has also served as a technical committee member of various conferences such as IEEE Asian Solid-State Circuits Conference (A-SSCC), IEEE International Symposium on Circuits and Systems (ISCAS), IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), etc. He was the Chair of IEEE SSCS Singapore Chapter in 2015~2016. He is a senior member of IEEE.
Low power and high performance digital, mixed-mode, and memory circuit design, ultra-low voltage sub-threshold circuit design for energy efficient systems, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs.
 
  • Advanced ReRAM Technology For Embedded Systems
  • Demonstrators and System Integration
  • Energy-Efficient and Endurable Memory Interface Circuits (WP 1 and WP3)
  • Memristive Halide Perovskites for Next Generation Embedded Neuromorphic Computing
  • Origami AlGaN/GaN Optoelectronics for Ultraviolet Hemispherical Electronic Eye Systems
  • Project ARIDEN
  • Resistive Memory Endurance Enhancement Utilizing Smart Mitigation and Recovery Techniques
US 2018/0019661 A1: Device And Method For Energy Harvesting Using A Self-Oscillating Power-On-Reset Start-Up Circuit With Auto-Disabling Function (2018)
Abstract: Device and method for energy harvesting using a self-oscillating power-on reset start-up circuit. The device for energy harvesting comprises a start-up circuit for generating self-oscillation and initial boosting of an input voltage from an energy source during a start-up phase; a main boost circuit for boosting the input voltage during a steady state phase; a clock generator circuit for generating clock signals which control voltage boosting of the main boost circuit during the steady state phase; and a switching circuit coupled to the start-up circuit, the main boost circuit and the clock generator circuit for switching powering of the clock generator circuit between the start-up circuit and the main boost circuit such that the clock generator circuit is powered by only one of the start-up circuit and the main boost circuit at any point in time.