Academic Profile : Faculty

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Prof Chang, Joseph Sylvester
Professor, School of Electrical & Electronic Engineering
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Joseph Chang received the PhD degree from the Department of Otolaryngology, Faculty of Medicine, The University of Melbourne, Australia. He is presently with the School of Electrical and Electronics Engineering, Nanyang Technological University (NTU), Singapore, and is adjunct at the Texas A&M University (USA). He was the former Associate Dean (Research and Graduate Studies), College of Engineering, NTU.

He has received numerous research grants including from DARPA (USA), European Union, industrial grants from multinational corporations, Singapore’s A*STAR, MoE, etc. He has active research international collaborations, including with the California Institute of Technology (Caltech), Massachusetts Institute of Technology (MIT) and Weill Medical College, Cornell University.

He has founded two start-ups.

He is also active in professional societies, including having served as General Chair of several IEEE-NIH (National Institutes of Health, USA) and international conferences/workshops. He was a Guest Editor of the Proceedings of the IEEE, is the Editor of the Open Column (IEEE Circuits and Systems magazine), and associate editor of the IEEE Transactions of Circuits and Systems journal.
Joseph Chang is multi-disciplinary engineer with research encompassing core CAS-related fields including analog, digital and aerospace circuits/systems; biomedical/life-sciences related-fields; and the emerging printed-electronics. He received the B.Eng (ECE) from Monash University, and Ph.D. from the Department of Otolaryngology, Faculty of Medicine, University of Melbourne, and has two-years IC-related industrial-experience. He is currently with the Nanyang Technological University, Singapore (and Adjunct at Texas A&M).

He has contributed to senior university administration and to ECE undergraduate/graduate education. He was the inaugural Associate-Dean of Research-and-Graduate-Studies at the 660 faculty-strong College-of-Engineering. For undergraduate education, he emphasized on promoting and instilling undergraduates’ interest in ECE, including being the chair of the Undergraduate-Research-Experience-on-Campus and Undergraduate-Research-Opportunities-Program programs, chaired Orientation-Programs and national-level undergraduate-conferences, and has given several talks in high-schools.

In the IEEE, he contributed to both core and multi-disciplinary fields, including as Guest-Editor of the Proceedings-of-the-IEEE on ‘Computational System-Biology’, Guest-Editor of the CAS-Magazine on ‘Special-Issue on Life-Sciences’, Editor of the CAS-Magazine’s Open-Column, Chairperson of the IEEE-NIH Life-Sciences-Systems-and-Applications (LiSSA) Workshop, Chairperson of two IEEE-NIH CAS-Medical-and-Environmental (CASME) Workshops, Chairperson of the LiSSA Technical-Committee, Associate-Editor of IEEE TCAS-I (3-terms) and -II, Associate-Editor of the IEEE CAS-Magazine, Distinguished-Lecturer, etc. Of specific interest, he organized the successful merging of the BioCAS and LiSSA technical-committees, largely for CAS’s concerted/united life-sciences efforts. He was instrumental in several non-IEEE establishments’ engagement in CAS’s activities, including other IEEE societies, National-Institutes-of-Health, Telemedicine-and-Advanced-Technology-Research-Center, American-Institute-of-Medical-and-Bioengineering, etc. Impact thereto includes NIH’s request for each of their 27 institutes a copy of the aforesaid CAS-magazine’s special-issue, representation by different IEEE societies at the IEEE-NIH workshops and NIH financial support for CASME.

He has published over 200 referee-reviewed publications (primarily in IEEE) and has over 20 patents (awarded/pending). In the field of ‘Class-D amplifier’, he has the most number of publications in the IEEE; and the top-ranked paper (excluding patents) and four of the top six papers in ‘Digital Class-D Amplifier’ in Google Scholar. He has received numerous grants from local and international funding-agencies (including DARPA and the EU) and from industry, amounting to >US$10M. He has founded two startups, and has designed numerous ECE-related products for industry.

His research interests are largely emerging technologies, including bioengineering, microfluidics, audiology, psychoacoustics, and analog and digital circuit designs. He leads a group of 25 researchers - externally funded - including from DARPA (USA) and from the European Union. Some description of his work may be found in the following editorials of the Proceedings of the IEEE and the IEEE Circuits and Systems Magazine (where he served as a Guest Editor):

J. Chang, S. Wong, R. Newcomb and P. Häfliger, ‘Third Revolution in Medicine – the Convergence of Life Sciences with Physical Sciences, Mathematics and Engineering’, IEEE Circuits and Systems Magazine, Special Issue on Life Sciences, Aug 2012

S. Wong, M. Ogorzalek and J. Chang, ‘Editorial on the Special Issue on Computational Systems Biology’, The Proceedings of the IEEE, Aug 2008
  • A New-Generation Envelope Tracking Modulator for Radio-Frequency Communications Devices (including the Internet-of-Things): Higher Power-Efficiency, Wider Bandwidth and 'Open' Platform
  • Enabling COTS AI Modules to feature Ultra-Low Soft Error Rate - A Novel Plug-and-Play Radhard/ Tolerant Error-Detection-and-Correction (EDAC) Module
  • Enabling COTS Systems for New and Next-Generation Satellites/Constellations: Machine-Learning - System Latchup Detection and Protection (ML-SLDAP)
  • Heterogeneously Integrated Very High-Frequency DC-DC Converter for Ultra-Subminiature (Cubic-Millimetre) Applications
  • Integrated Power Management System for the Next-Generation Internet-of-Things
  • Mutual Interaction between Two Pairs of Electrodes with Distinct Electrochemical Potentials
  • Use-case-oriented study on novel sampling methods for increasing receiver dynamic range (ROMULAN)
US 2018/0214878 A1: Testing Device, Microfluidic Chip And Nucleic Acid Testing Method (2021)
Abstract: A testing device is provided. The testing device includes a capturing tool and a microfluidic chip having a plurality of chambers connected in a network, a sample receiving port connected to the network, and a guide structure configured to receive the capturing tool, wherein the capturing tool is configured to capture sample in a distal position from the guide structure and further configured to transfer the captured sample to the sample receiving port in a proximal position from the guide structure.

US 2019/0355766 A1: A Method Of Forming A Multilayer Structure For A Pixelated Display And A Multilayer Structure For A Pixelated Display (2020)
Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.

US 2019/0305048 A1: A Method Of Fabricating An Electrical Circuit Assembly On A Flexible Substrate (2020)
Abstract: A method of fabricating an electrical circuit assembly on a flexible substrate comprises: identifying one or more bending-sensitive elements of an electrical circuit assembly, each bending-sensitive element having a performance that varies when said bending-sensitive element is flexed; splitting said one or more bending-sensitive elements into a first portion and a second portion, wherein the first portion and the second portion are functionally equivalent and together equate to said bending-sensitive element; printing the first portion of said bending-sensitive element on a first surface of the flexible substrate; printing the second portion of said bending-sensitive element on a second surface of the flexible substrate, diametrically opposite the first portion such that bending of the flexible substrate has an opposite effect on each of the first and second portions thereby serving to substantially cancel the effect on each portion out; and electrically connecting the first portion and the second portion.

US 2017/0237250 A1: Electronic Circuit for Single-Event Latch-Up Detection And Protection (2020)
Abstract: An electronic circuit for single-event latch-up (SEL) detection and protection of a target integrated circuit (IC) is disclosed. The circuit comprises: a first detector configured for detecting an absolute load current (i) and comparing the absolute load current (i) with a threshold current (ith); a second detector configured for detecting a rate of change of load current (di/dt) and comparing the rate of change of load current (di/dt) with a threshold current change rate (di/dt)th; and a determination module for triggering a power shut-down to the target IC if the absolute load current (i) exceeds the threshold current (ith) and/or the rate of change of load current (di/dt) exceeds the threshold current change rate (di/dt)th.

US 2016/0211809 A1: Ultra-High-Fidelity -cum- Ultra-Noise-Immunity Audio Class D Amplifiers (2018)
Abstract: A method (300) of generating a pulse width modulation (PWM) signal for an analog amplifier, the amplifier arranged to receive an amplifier input signal having a magnitude, is disclosed. The method comprises receiving (302) a modulator input signal, which is associated with the amplifier input signal; and using (304) the modulator input signal to modulate a carrier to produce the PWM signal, wherein the carrier's frequency varies in dependence on the magnitude of the amplifier input signal. A related pulse width modulator is also disclosed.

US 2013/0113522 A1: Asynchronous-Logic Circuit For Full Dynamic Voltage Control (2014)
Abstract: Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation.

US 2021/0250002 A1: Supply Modulator, Power Amplifier Having The Same, Method For Controlling The Same, And Method For Controlling The Power Amplifier (2022)
Abstract: A supply modulator is provided, having a first amplifier circuit configured to generate a first electrical signal, a second amplifier circuit configured to generate a second electrical signal, the first and second electrical signals being for driving an electrical load, and a control circuit electrically coupled to the first and second amplifier circuits wherein the control circuit is configured to generate a pulsed electrical signal and to supply an output control signal to the second amplifier circuit for controlling generation of the second electrical output signal, wherein the supply modulator is configured to operate in two modes of operation, for the first amplifier circuit to generate the first electrical signals in response to quiescent current of the first amplifier circuit, for the control circuit to generate a modulated electrical signal in accordance with a clock signal in one mode, and, for the second amplifier circuit to operate at different frequencies.

US 2021/0083665 A1: Circuit Arrangements And Methods For Forming The Same (2022)
Abstract: A circuit arrangement is provided, having a first circuit configured to receive an input signal, and a second circuit configured to provide an output signal, wherein the first circuit includes a first pull-up network having a first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other, and a first pull-down network having a first transistor of the first conductivity type and a second transistor of the second conductivity type electrically coupled to each other, wherein the second circuit includes a second pull-up network having a first transistor of the first conductivity type, and a second pull-down network having a second transistor of the second conductivity type, wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other.