Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/97318
Title: The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance : a comparative study
Authors: Liao, H.
Goh, L. N. L.
Liu, H.
Sudijono, J. L.
Elgin, Q.
Sanford, C.
Lee, Pooi See
Keywords: DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Thin films
Issue Date: 2004
Source: Liao, H., Lee, P. S., Goh, L. N. L., Liu, H., Sudijono, J. L., Elgin, Q., & Sanford, C. (2004). The impact of etch-stop layer for borderless contacts on deep submicron CMOS device performance—a comparative study. Thin Solid Films, 462-463, 29-33.
Series/Report no.: Thin solid films
Abstract: The impact of etch-stop layers (ESLs) of borderless contact (BLC) on transistor characteristics, especially for NMOSFETs, was studied concerning on the ESL-induced mechanical stress. Two new ESL schemes using dual etch-stop layers: (scheme A) SiON (bottom)/SiN (top) and (scheme B) SiN (bottom)/SiON (top) were studied and implemented into device fabrication. The electrical performance of the N- and PMOSFETs was characterized. It has been found that by using scheme A, a 2.7% improvement of Ion versus Ioff margin as compared with the single-layer process is achieved on NMOSFETs. The scheme A results in a loss of the PMOS margin by 1.4%, which is still within the specifications. However, scheme B, which uses a SiN as the bottom layer, presents a slightly less improvement of process margin (1.7%) on NMOSFETs with much larger loss of process margin (2.3%) on PMOSFETs. Our results suggest that optimization of ESL for borderless contact could play an important role in determining transistor performance for deep submicron CMOS.
URI: https://hdl.handle.net/10356/97318
http://hdl.handle.net/10220/10502
ISSN: 0040-6090
DOI: http://dx.doi.org/10.1016/j.tsf.2004.05.035
Rights: © 2004 Elsevier B.V.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:MSE Journal Articles

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