dc.contributor.authorDarmawan, P.
dc.contributor.authorYuan, C. L.
dc.contributor.authorLee, Pooi See
dc.date.accessioned2013-06-20T03:01:54Z
dc.date.available2013-06-20T03:01:54Z
dc.date.copyright2006en_US
dc.date.issued2006
dc.identifier.citationDarmawan, P., Yuan, C. L., & Lee, P. S. (2006). Trap-controlled behavior in ultrathin Lu2O3 high-k gate dielectrics. Solid State Communications, 138(12), 571-573.en_US
dc.identifier.issn0038-1098en_US
dc.identifier.urihttp://hdl.handle.net/10220/10504
dc.description.abstractAmorphous Lu2O3 high-k gate dielectrics were grown directly on n-type (100) Si substrates by the pulsed laser deposition (PLD) technique. High-resolution transmission electron microscope (HRTEM) observation illustrated that the Lu2O3 film has amorphous structure and the interface with Si substrate is free from amorphous SiO2. An equivalent oxide thickness (EOT) of 1.1 nm with a leakage current density of 2.6×10−5 A/cm2 at 1 V accumulation bias was obtained for 4.5 nm thick Lu2O3 thin film deposited at room temperature followed by post-deposition anneal (PDA) at 600 °C in oxygen ambient. The effects of PDA process and light illumination were studied by capacitance–voltage (C–V) and current density–voltage (J–V) measurements. It was proposed that the net fixed charge density and leakage current density could be altered significantly depending on the post-annealing conditions and the capability of traps to trap and release charges.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesSolid state communicationsen_US
dc.rights© 2006 Elsevier Ltd.en_US
dc.subjectDRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Thin films
dc.titleTrap-controlled behavior in ultrathin Lu2O3 high-k gate dielectricsen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Materials Science and Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1016/j.ssc.2006.05.003


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