Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/95912
Title: A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector
Authors: Tan, Yung Sern
Yeo, Kiat Seng
Boon, Chirn Chye
Do, Manh Anh
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2011
Source: Tan, Y. S., Yeo, K. S., Boon, C. C., & Do, M. A. (2012). A dual-loop clock and data recovery circuit with compact quarter-rate CMOS linear phase detector. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(6), 1156-1167.
Series/Report no.: IEEE transactions on circuits and systems I : regular papers
Abstract: This paper presents a 5-Gb/s dual-loop clock and data recovery (CDR) circuit with a compact quarter-rate linear phase detector (PD). The proposed PD not only reduces the complexity of the circuit structure but also employs an UP pulse-widening technique to circumvent the problem of existing narrow UP pulses. Meanwhile, it has the least number of output signals among all the other linear PDs with UP pulse-widening technique. It also provides a data recovery circuit to de-multiplex the input data with no systematic phase offset. An unbalanced charge pump (CP) is also proposed to compensate the unbalanced pulse-width of UP and DN pulses as well as the unequal number of signal between UP and DN pulses. A detailed propagation delay analysis and a set of equations to predict the characteristic curve of the proposed PD is given. In addition, a lock detector with hysteresis property is implemented to ensure proper switching of the loops. Fabricated in 0.18- μm CMOS technology, the circuit shows that the peak-to-peak jitter of the recovered clock is 30.4-ps and it consumes 71.9-mW from a 1.8 V supply.
URI: https://hdl.handle.net/10356/95912
http://hdl.handle.net/10220/11325
ISSN: 1549-8328
DOI: 10.1109/TCSI.2011.2173387
Rights: © 2011 IEEE.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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