Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/95909
Title: A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS
Authors: Low, Jeremy Yung Shern
Chang, Chip Hong
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Low, J. Y. S., & Chang, C. H. (2012). A VLSI efficient programmable power-of-two scaler for 2n-1, 2n,2n+1 RNS. IEEE Transactions on Circuits and Systems I : Regular Papers, 59(12), 2911-2919.
Series/Report no.: IEEE transactions on circuits and systems I : regular papers
Abstract: Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic and is also commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. While this operation can be readily performed in binary number system, it is extremely difficult to implement in residue number system (RNS). In the absence of an efficient solution to scale an integer directly in residue domain by a programmable power-of-two factor, improvised architecture by cascading fixed RNS scaling-by-two blocks has been previously presented. However, its area complexity and time complexity are worse than a hybrid solution leveraging on binary shifting through efficient residue-to-binary and binary-to-residue conversions. This paper presents a new algorithm for scaling in {2n - 1,2n,2n + 1} RNS by a programmable power-of-two factor. The proposed scaling algorithm breaks the inter-modulus dependency and produces a parallel architecture incurring no more than two logarithmic shifters, one-stage of carry-save adder and a modulo adder in any modulus channel. Comparing with the only available and most efficient hybrid programmable power-of-two scaler for the same moduli set, our proposed design has not only significantly reduced the critical path delay by 52.2%, 52.8%, 53.1%, and 53.2% for n = 5 , 6, 7, and 8, respectively, but also cut down the area by 14.1% on average based on CMOS 0.18 μm standard cell based implementation. In addition, our proposed design has effectively reduced the total power consumption by 43.8% and the leakage power by 20.6% on average.
URI: https://hdl.handle.net/10356/95909
http://hdl.handle.net/10220/11327
ISSN: 1549-8328
DOI: http://dx.doi.org/10.1109/TCSI.2012.2206491
Rights: © 2012 IEEE.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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