Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/95955
Title: Sensing margin enhancement techniques for ultra-low-voltage SRAMs utilizing a bitline-boosting current and equalized bitline leakage
Authors: Do, Anh Tuan
Nguyen, Truc Quynh
Yeo, Kiat Seng
Kim, Tony Tae-Hyoung
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2013
Source: Do, A. T., Nguyen, T. Q., Yeo, K. S., & Kim, Tony T. T.-H. (2012). Sensing Margin Enhancement Techniques for Ultra-Low-Voltage SRAMs Utilizing a Bitline-Boosting Current and Equalized Bitline Leakage. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(12), 868-872.
Series/Report no.: IEEE transactions on circuits and systems II : express briefs
Abstract: A small bitline sensing margin is one of the most challenging design obstacles for reliable ultra-low-voltage static random access memory (SRAM) implementation. This paper presents design techniques for bitline sensing margin enhancement using decoupled SRAMs. The proposed bitline-boosting current scheme improves the bitline sensing margin at a given bitline configuration. The bitline sensing margin can be further augmented by equalizing bitline leakage. Simulation using a 40-nm CMOS process shows that the proposed techniques achieve larger bitline sensing margin, wider operating temperature and supply range, and a larger number of cells per bitline.
URI: https://hdl.handle.net/10356/95955
http://hdl.handle.net/10220/11361
ISSN: 1549-7747
DOI: http://dx.doi.org/10.1109/TCSII.2012.2231014
Rights: © 2013 IEEE.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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