dc.contributor.authorLin, Tong
dc.contributor.authorChong, Kwen-Siong
dc.contributor.authorChang, Joseph Sylvester
dc.contributor.authorGwee, Bah Hwee
dc.contributor.authorShu, Wei
dc.date.accessioned2013-07-24T08:12:25Z
dc.date.available2013-07-24T08:12:25Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.citationLin, T., Chong, K.-S., Chang, J. S., Gwee, B. H., & Shu, W. (2012). A robust asynchronous approach for realizing ultra-low power digital Self-Adaptive VDD Scaling system. 2012 IEEE Subthreshold Microelectronics Conference (SubVT), 1-3.en_US
dc.identifier.urihttp://hdl.handle.net/10220/12119
dc.description.abstractSelf-Adaptive VDD Scaling (SAVS) technique achieves power/energy reduction by dynamically scaling VDD for the prevailing conditions. However, when applied in sub-threshold (sub-Vt) region, robustness issues need to be addressed due to the severe delay uncertainty associated with sub-Vt Process, Voltage, and Temperature (PVT) variations. To ensure robustness for sub-Vt SAVS, we adopt the asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) approach. To address the usual power/energy overheads associated with conventional async QDI systems, we further propose a hardware-simplified version of QDI (`pseudo-QDI') with an easy-to-met implicit timing. Prototype ICs embodying async filter banks realized in both the conventional QDI and pseudo-QDI have demonstrated the extreme robustness of the proposed approach against sub-Vt PVT variations. Measurement results further suggest pseudo-QDI's energy (~40% lower) and area (~1.34× smaller) advantages as compared to its conventional QDI counterpart.en_US
dc.language.isoenen_US
dc.rights© 2012 IEEE.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleA robust asynchronous approach for realizing ultra-low power digital Self-Adaptive VDD Scaling systemen_US
dc.typeConference Paper
dc.contributor.conferenceIEEE Subthreshold Microelectronics Conference (2012 : Waltham, US)en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/SubVT.2012.6404298


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