Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration
Clarke, Christopher T.
Date of Issue2012
International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (7th : 2012 : York, UK)
School of Computer Engineering
Centre for High Performance Embedded Systems
Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the advantages of runtime reconfiguration on reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework incorporates a hierarchical loop partitioning strategy that leverages FPGA-aware merging of custom instructions to: 1) maximize the reconfigurable logic block utilization in each configuration, and 2) reduce the runtime reconfiguration overhead. Experimental results show that the proposed strategy leads to over 39% average reduction in runtime reconfiguration overhead for partial runtime reconfiguration. In addition, the proposed strategy leads to an average performance gain of over 32% and 34% for full and partial runtime reconfiguration respectively.
DRNTU::Engineering::Computer science and engineering
© 2012 IEEE.