Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/99047
Title: Retention time characterization and optimization of logic-compatible embedded DRAM cells
Authors: Do, Anh Tuan
Yi, He
Yeo, Kiat Seng
Kim, Tony Tae-Hyoung
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Abstract: Logic-compatible 2T and 3T embedded DRAMs (eDRAM) have recently gained their popularity in embedded applications because of their high density and good voltage margin. The most important design requirements in eDRAM cells are cell area, data retention time and read speed. In this paper, we present an in-depth analysis on the data retention time of various logic-compatible eDRAM cells, followed by the effects of several design factors on the retention time. A systematic methodology is proposed for enhancing the retention time of the eDRAM cells. Simulation results using a standard 65nm CMOS technology show that the optimization process improves the data retention time more than 3x. Finally, the number of read operations per retention period is estimated to show the effectiveness of each eDRAM cell. Analysis demonstrates that although the 2T eDRAM cell has a shorter retention time than the conventional 3T cell, it has better effectiveness due to the faster read operation.
URI: https://hdl.handle.net/10356/99047
http://hdl.handle.net/10220/12575
DOI: 10.1109/ACQED.2012.6320471
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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