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|Title:||Maximization of SRAM energy efficiency utilizing MTCMOS technology||Authors:||Wang, Bo
Kim, Tony Tae-Hyoung
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2012||Abstract:||Higher-Vth devices in the cross-coupled latches and the write access transistors, and lower-Vth devices in the read ports are preferred for reducing leakage current without sacrificing performance. However, at ultra-low supply voltage levels, higher-Vth devices can retard or nullify energy efficiency due to substantially slower write speed than read. This paper presents energy efficiency maximization techniques for 8T SRAMs utilizing multi-threshold CMOS (MTCMOS) technology and various design techniques. Simulation results using a commercial 65 nm technology show that the SRAM energy efficiency can improved up to 33x through MTCMOS and prior power reduction and performance boosting techniques.||URI:||https://hdl.handle.net/10356/99114
|DOI:||10.1109/ACQED.2012.6320472||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Conference Papers|
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