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|Title:||An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS||Authors:||Shang, Yang
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2012||Source:||Shang, Y., Cai, D., Fei, W., Yu, H., & Ren, J. (2012). An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS. 2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 47-49.||Abstract:||An ultra low power direct-conversion receiver is demonstrated for V-band 60GHz applications in 65nm CMOS process. The power consumption is significantly reduced by the design of low-power low noise amplifier (LNA), transconductance mixer and variable gain amplifier (VGA). A compact quadrature-hybrid coupler is developed for transconductance mixer for the reduction of both power and area. The proposed receiver (0.34mm2 chip area) is measured with 8mW power, the minimum single-side-band (SSB) noise figure (NF) of 4.9dB, and the maximum power conversion gain of 55dB.||URI:||https://hdl.handle.net/10356/99096
|DOI:||10.1109/RFIT.2012.6401609||Rights:||© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/RFIT.2012.6401609].||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Conference Papers|
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