dc.contributor.authorChen, Yi-Chung
dc.contributor.authorWang, Wenhua
dc.contributor.authorLi, Hai
dc.contributor.authorZhang, Wei
dc.date.accessioned2013-08-06T02:54:44Z
dc.date.available2013-08-06T02:54:44Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.urihttp://hdl.handle.net/10220/13024
dc.description.abstractWe demonstrates a novel Field-Programmable Gate Array (FPGA) structure based on Resistive Random Access Memory (RRAM) system. RRAM is a non-volatile memory device which is compatible to CMOS Back End of Line (BEOL) process with only 4F2 area per cell. We use a 1R system memory for logic element, Look-Up-Table (LUT), with three dimension stacking structure. The proposed 2R memory system is for routing elements, Switch Block (SB) and Connection Block (CB), with Complementary Resistive Switches (CRS) structure. Both three dimension stacking and CRS structure are crossbar-like structure to further improve density of the FPGA. The proposed design is different from modern FPGA with Static Random Access Memory (SRAM) system, RRAM-based FPGA has benefits of non-volatility, smaller area, and flexibility of configuration. A bit-addressable LUT is introduced with function of run-time programming memory cells of LUT, which is also known as Distributed Random Access Memory (D-RAM). Based on our simulation results, 62.7% of area reduction and 34% of delay improvement can be achieved compared to the conventional FPGA.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Computer science and engineering
dc.titleNon-volatile 3D stacking RRAM-based FPGAen_US
dc.typeConference Paper
dc.contributor.conferenceInternational Conference on Field Programmable Logic and Applications (22nd : 2012 : Oslo, Norway)en_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/FPL.2012.6339206


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