Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/97923
Title: | A PAE of 17.5% Ka-band balanced frequency doubler with conversion gain of 20 dB | Authors: | Li, Jiankang Lu, Zhong Xiong, Yong-Zhong Hou, Debin Wang, Ren Goh, Wang Ling Wu, Wen |
Keywords: | DRNTU::Engineering::Electrical and electronic engineering | Issue Date: | 2012 | Conference: | IEEE Radio Frequency Integrated Circuits Symposium (2012 : Montreal, Canada) | Abstract: | A frequency doubler from 27 to 41 GHz fabricated in 0.13-μm SiGe BiCMOS technology with a maximum output power of 8 dBm and a power added efficiency (PAE) of 17.5% at dc power consumption of 35 mW is presented. It consists of a balun, a driver amplifier (DA), a common-base (CB) core and a medium power amplifier. The CB topology with balun is designed for wider bandwidth and better matching. The measured results showed that the doubler presents a gain of 16.8-19.8 dB, an output power of 1.3-4.3 dBm, and a fundamental rejection of better than 25.7 dB from 27 to 41 GHz with -15.5 dBm input power. The chip size is 0.75 × 0.45 mm2. | URI: | https://hdl.handle.net/10356/97923 http://hdl.handle.net/10220/13233 |
DOI: | 10.1109/RFIC.2012.6242296 | Schools: | School of Electrical and Electronic Engineering | Fulltext Permission: | none | Fulltext Availability: | No Fulltext |
Appears in Collections: | EEE Conference Papers |
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