Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/100633
Title: Low-energy and area-efficient tri-level switching scheme for SAR ADC
Authors: Yuan, C.
Lam, Y.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Yuan, C.,& Lam, Y. (2012). Low-energy and area-efficient tri-level switching scheme for SAR ADC. Electronics Letters, 48(9), 482.
Series/Report no.: Electronics letters
Abstract: A novel low-energy tri-level switching scheme for low-power successive approximation register (SAR) ADC is proposed. With the input common-mode voltage (Vcm) designed to be exactly half of the reference voltage (Vref ), the switching energy of the proposed switching scheme is reduced by 96.89% as compared with the conventional architecture. Besides the large energy saving, the proposed switching scheme also reduces the number of capacitors in the ADC capacitor array by 75%, which in turn results in an area-efficient SAR ADC.
URI: https://hdl.handle.net/10356/100633
http://hdl.handle.net/10220/13270
ISSN: 0013-5194
DOI: http://dx.doi.org/10.1049/el.2011.4001
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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