A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement
Kim, Tony Tae-Hyoung
Date of Issue2012
European Solid State Device Research Conference (2012 : 42th)
School of Electrical and Electronic Engineering
A 5.61 pJ, 16 kb 9T SRAM is implemented in 65nm CMOS technology. A single-ended equalized bitline scheme is proposed to improve both read bitline voltage swing and sensing timing window. A fast local write-back allows the half-select-free write operation without performance degradation. The test chip shows a minimum operating voltage of 0.24V and a minimum energy of 5.61pJ at 0.3V.
DRNTU::Engineering::Electrical and electronic engineering