dc.contributor.authorCheah, Hui Yan
dc.contributor.authorFahmy, Suhaib A.
dc.contributor.authorMaskell, Douglas L.
dc.date.accessioned2013-10-04T07:55:44Z
dc.date.available2013-10-04T07:55:44Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.citationCheah, H. Y., Fahmy, S. A., & Maskell, D. L. (2012). iDEA: A DSP block based FPGA soft processor. 2012 International Conference on Field-Programmable Technology (FPT), 151 - 158.
dc.identifier.urihttp://hdl.handle.net/10220/16290
dc.description.abstractThis paper presents a very lean DSP Extension Architecture (iDEA) soft processor for Field Programmable Gate Arrays (FPGAs). iDEA has been built to be as lightweight as possible, utilising the run-time flexibility of the DSP48E1 primitive in Xilinx FPGAs to serve as many processor functions as possible. We show how the primitive's flexibility can be leveraged within a general-purpose processor, what additional circuitry is needed, and present a full instruction-set architecture. The result is a very compact processor that can run at high speed, while executing a full gamut of general machine instructions. We provide results for a number of simple applications, and show how the processor's resource requirements and frequency compare to a Xilinx MicroBlaze soft core. Based on the DSP48E1, this processor can be deployed across next-generation Xilinx Artix-7, Kintex-7, and Virtex-7 families.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Computer science and engineering
dc.titleiDEA : a DSP block based FPGA soft processoren_US
dc.typeConference Paper
dc.contributor.conferenceInternational Conference on Field-Programmable Technology (2012 : Seoul, Korea)en_US
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/FPT.2012.6412128


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