Please use this identifier to cite or link to this item:
|Title:||DELTRON : neuromorphic architectures for delay based learning||Authors:||Hussain, Shaista
Hamilton, Tara Julia
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2012||Source:||Hussain, S., Basu, A., Wang, M., & Hamilton, T. J. (2012). DELTRON : neuromorphic architectures for delay based learning. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp.304-307.||Abstract:||We present a neuromorphic spiking neural network, the DELTRON, that can remember and store patterns by changing the delays of every connection as opposed to modifying the weights. The advantage of this architecture over traditional weight based ones is simpler hardware implementation without multipliers or digital-analog converters (DACs). The name is derived due to similarity in the learning rule with an earlier architecture called Tempotron. We present simulations of memory capacity of the DELTRON for different random spatio-temporal spike patterns and also present SPICE simulation results of the core circuits involved in a reconfigurable mixed signal implementation of this architecture.||URI:||https://hdl.handle.net/10356/101646
|DOI:||http://dx.doi.org/10.1109/APCCAS.2012.6419032||Rights:||© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/APCCAS.2012.6419032].||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Conference Papers|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.