dc.contributor.authorXiaodan, Zou
dc.contributor.authorLei, Liu
dc.contributor.authorTan, Yung Sern
dc.contributor.authorJe, Minkyu
dc.contributor.authorYeo, Kiat Seng
dc.date.accessioned2013-10-10T03:03:36Z
dc.date.available2013-10-10T03:03:36Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.citationXiaodan, Z., Lei, L., Tan, Y. S., Je, M., & Yeo, K. S. (2012). Integrated circuits design for neural recording sensor interface. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp.17-20.
dc.identifier.urihttp://hdl.handle.net/10220/16343
dc.description.abstractNeural signal recording is attracting more and more attention, as it provides an necessary approach to read brain activities, understand the brain operation and restore the lost motor function of the body. One of the most important modules in the neural recording system is the sensor interface IC, which captures, amplifies, filters, and digitizes the weak neural signal. In order to preserve free movement of the subject under testing and minimize the risk of infection, the sensor interface IC is usually implanted under the skin or skull with wireless transmission. The nature of the neural signal and its recording scenarios impose rigid design specifications to the sensor interface IC, such as low noise, low power, low cut-off frequency and minimum chip size. Many designs have been reported recently to tackle these challenges in neural recording system. In this paper, design techniques for neural recording sensor interface IC will be introduced, including the design of system architecture and neural amplifier. Methods to realize low power, low noise and low cut-off frequency are investigated. In addition, the methods to achieve system power and area optimization are also discussed.en_US
dc.language.isoenen_US
dc.rights© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/APCCAS.2012.6418960].
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleIntegrated circuits design for neural recording sensor interfaceen_US
dc.typeConference Paper
dc.contributor.conferenceIEEE Asia Pacific Conference on Circuits and Systems (2012 : Kaohsiung, Taiwan)en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/APCCAS.2012.6418960
dc.description.versionAccepted version


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