Low-power high-speed dual-modulus prescaler for Gb/s applications
Yeo, Kiat Seng
Date of Issue2012
IEEE Asia Pacific Conference on Circuits and Systems (2012 : Kaohsiung, Taiwan)
School of Electrical and Electronic Engineering
This paper present a low-power 10-GHz divide-by-3/4 prescaler for 60-GHz high data rate short range wireless communication systems. Design techniques utilized to optimize the power consumption are addressed. The critical circuit, current-mode-logic (CML) blocks, are optimized to achieve high speed and low power consumption simultaneously. The prescaler is implemented in a low-cost commercial 0.18-μm SiGe BiCMOS technology. The maximum operating frequency is up to 10 GHz, with 8.6 mW power consumption in 1.8 V supply. The core area is 190 μm×120 μm.
DRNTU::Engineering::Electrical and electronic engineering