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|Title:||A novel memristor-based rSRAM structure for multiple-bit upsets immunity||Authors:||Wang, Liyun
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Applications of electronics||Issue Date:||2012||Source:||Wang, L., Zhang, C., Chen, L., Lai, J., & Tong, J. (2012). A novel memristor-based rSRAM structure for multiple-bit upsets immunity. IEICE electronics express, 9(9), 861-867.||Series/Report no.:||IEICE electronics express||Abstract:||A radiation hardened resistive SRAM structure (rSRAM) is proposed for the SRAM-based FPGAs in this paper. The rSRAM extends the conventional 6T SRAM structure by connecting memristors between the information nodes and drains of the transistors which compose cross-coupled invertors. With memristors connected to drains of OFF transistors configured to high resistance state while others configured to low resistance state forming stable voltage dividing path, the rSRAM structure is immune to both multiple-node upsets and multiple-bit upsets (MBUs). The simulation result demonstrates that rSRAM cell can tolerate simultaneous disruptions affecting all sensitive nodes with an LET (Liner Energy Transfer) of 100Mev-cm2/mg.||URI:||https://hdl.handle.net/10356/100285
|DOI:||10.1587/elex.9.861||Rights:||© 2012 IEICE. This paper was published in IEICE electronics express and is made available as an electronic reprint (preprint) with permission of IEICE. The paper can be found at the following official DOI: [http://dx.doi.org/10.1587/elex.9.861]. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Journal Articles|
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