Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/102296
Title: An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS
Authors: Edward, Alexander
Chan, Pak Kwong
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Issue Date: 2012
Source: Edward, A., & Chan, P. (2012). An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS. IEICE transactions on electronics, 95(4), 733-743.
Series/Report no.: IEICE transactions on electronics
Abstract: This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6V. The designed IA achieves 30dB of closed-loop gain, 101dB of common-mode rejection ratio (CMRR) at 50Hz, 80dB of power-supply rejection ratio (PSRR) at 50Hz, thermal noise floor of 53.4 nV/√Hz, current consumption of 14µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6V supply from a 0.8-1.0V energy harvesting power source. It achieves power supply rejection (PSR) of 42dB at frequency of 1MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100Hz sinusoidal maximum input signal, bandwidth of 2kHz, and power consumption of 51.2µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18µm CMOS process.
URI: https://hdl.handle.net/10356/102296
http://hdl.handle.net/10220/16511
ISSN: 0916-8524
DOI: http://dx.doi.org/10.1587/transele.E95.C.733
Rights: © 2012 The Institute of Electronic, Information and Communication Engineers. This paper was published in IEICE transactions on electronics and is made available as an electronic reprint (preprint) with permission of The Institute of Electronic, Information and Communication Engineers. The paper can be found at the following official DOI: [http://dx.doi.org/10.1587/transele.E95.C.733]. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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