dc.contributor.authorYu, Xiao Peng
dc.contributor.authorLu, Zhenghao
dc.contributor.authorLim, Wei Meng
dc.contributor.authorYeo, Kiat Seng
dc.date.accessioned2013-10-16T04:19:06Z
dc.date.available2013-10-16T04:19:06Z
dc.date.copyright2013en_US
dc.date.issued2013
dc.identifier.citationYu, X. P., Lu, Z.H., Lim, W.M., & Yeo, K.S. (2013). 0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique. Electronics letters, 49(7), 471-472.en_US
dc.identifier.issn0013-5194en_US
dc.identifier.urihttp://hdl.handle.net/10220/16515
dc.description.abstractA dual-modulus prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phase-locked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a wide-range operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide-by-2 and 3 dual-modulus prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesElectronics Lettersen_US
dc.rights© 2013 The Institution of Engineering and Technology.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.title0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking techniqueen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1049/el.2013.0584


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