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|Title:||3-D mesh-based optical network-on-chip for multiprocessor system-on-chip||Authors:||Ye, Yaoyao
|Keywords:||DRNTU::Engineering::Computer science and engineering::Information systems||Issue Date:||2013||Source:||Ye, Y., Xu, J., Huang, B., Wu, X., Zhang, W., Wang, X., Nikdast, M., Wang, Z., Liu, W.,& Wang, Z. (2013). 3-D mesh-based optical network-on-chip for multiprocessor system-on-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(4), 584-596.||Series/Report no.:||IEEE transactions on computer-aided design of integrated circuits and systems||Abstract:||Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to multiprocessor systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated technologies offer an opportunity to continue performance improvements with higher integration densities. In this paper, we present a 3-D mesh-based ONoC for MPSoCs, and new low-cost nonblocking 4 × 4, 5 × 5, 6 × 6, and 7 × 7 optical routers for dimension-order routing in the 3-D mesh-based ONoC. Besides, we propose an optimized floorplan for the 3-D mesh-based ONoC. The floorplan follows the regular 3-D mesh topology but implements all optical routers in a single optical layer. The floorplan is optimized to minimize the number of extra waveguide crossings caused when merging the 3-D ONoC to one optical layer. Based on a set of real applications and uniform traffic pattern, we develop a SystemC-based cycle-accurate NoC simulator and compare the 3-D mesh-based ONoC with the matched 2-D mesh-based ONoC and 2-D electronic NoC for performance and energy efficiency. Additionally, we quantitatively analyze thermal effects on the 3-D 8 × 8 × 2 mesh-based ONoC.||URI:||https://hdl.handle.net/10356/102583
|DOI:||http://dx.doi.org/10.1109/TCAD.2012.2228739||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||SCSE Journal Articles|
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