dc.contributor.authorManthena, Vamshi Krishna
dc.contributor.authorDo, Manh Anh
dc.contributor.authorBoon, Chirn Chye
dc.contributor.authorYeo, Kiat Seng
dc.date.accessioned2013-10-17T02:33:39Z
dc.date.available2013-10-17T02:33:39Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.citationManthena, V. K., Do, M. A., Boon, C. C., & Yeo, K. S. (2012). A low-power single-phase clock multiband flexible divider. IEEE transactions on very large scale integration (VLSI) systems, 20(2), 376-380.
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://hdl.handle.net/10220/16540
dc.description.abstractIn this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesIEEE transactions on very large scale integration (VLSI) systemsen_US
dc.rights© 2011 IEEEen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleA low-power single-phase clock multiband flexible divideren_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/TVLSI.2010.2100052


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