A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS
Date of Issue2013
IEEE International Solid-State Circuits Conference (2013 : San Francisco, California, US)
School of Electrical and Electronic Engineering
Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction.
DRNTU::Engineering::Electrical and electronic engineering