dc.contributor.authorHan, Dong
dc.contributor.authorZheng, Yuanjin
dc.contributor.authorRajkumar, Ramamoorthy
dc.contributor.authorDawe, Gavin
dc.contributor.authorJe, Minkyu
dc.date.accessioned2013-10-18T02:35:18Z
dc.date.available2013-10-18T02:35:18Z
dc.date.copyright2013en_US
dc.date.issued2013
dc.identifier.citationHan, D., Zheng, Y., Rajkumar, R., Dawe, G., & Je, M. (2013). A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 290 - 291.en_US
dc.identifier.urihttp://hdl.handle.net/10220/16578
dc.description.abstractConventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction.en_US
dc.language.isoenen_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleA 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOSen_US
dc.typeConference Paper
dc.contributor.conferenceIEEE International Solid-State Circuits Conference (2013 : San Francisco, California, US)en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/ISSCC.2013.6487739


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