dc.contributor.authorYi, Xiang
dc.contributor.authorBoon, Chirn Chye
dc.contributor.authorLiu, Hang
dc.contributor.authorLin, Jia Fu
dc.contributor.authorOng, Jian Cheng
dc.contributor.authorLim, Wei Meng
dc.identifier.citationYi, X., Boon, C. C., Liu, H., Lin, J. F., Ong, J. C., & Lim, W. M. (2013). A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.en_US
dc.description.abstractUnder the influence of increasing demand for high-data-rate communication systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method of using a divide-by-2 divider after a VCO with double LO frequency is popular in multi-GHz designs, but it is difficult to be realized at mm-Wave frequencies. Employing passive RC complex filters is another way to generate quadrature signals, but high power is required to compensate its loss. The conventional parallel-coupled QVCO seems to be a good choice for mm-Wave application. However, the approach suffers from poor phase noise. This work presents a fully integrated 57.9-to-68.3GHz frequency synthesizer, which employs an in-phase injection-coupled QVCO (IPIC-QVCO) to produce low-phase-noise quadrature signals with low power.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleA 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOSen_US
dc.typeConference Paper
dc.contributor.conferenceIEEE International Solid-State Circuits Conference (2013 : San Francisco, California, US)en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US

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