Wafer level silicon mould fabrication and imprinting of high density microstructures
Wong, T. I.
Ong, H. Y.
Lu, H. J.
Tse, M. S.
Quan, C. G.
Ng, S. H.
Date of Issue2013
School of Electrical and Electronic Engineering
Singapore Institute of Manufacturing Technology
Wafer level mould fabrication and its imprinting technology are of great interest for cost effective mass fabrication of nano or microsized patterns. Although the process for making a silicon mould involves only several steps such as photolithography, deep reactive ion etching (DRIE) and nanoimprinting, there are still many issues to be overcome in order to achieve uniformly imprinted patterns on the whole wafer. Taking a 4″ wafer full of high density 3 × 3 μm squares with a depth of 10 μm as an example, this paper investigates the pitfalls in silicon mould fabrication and imprinting, and provides feasible solutions as a good reference to researchers seeking to mass fabricate micron-sized patterns by thermal imprinting.
DRNTU::Engineering::Electrical and electronic engineering