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|Title:||A memory-efficient scalable architecture for lifting-based discrete wavelet transform||Authors:||Hu, Yusong
Jong, Ching Chuen
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2013||Source:||Hu, Y., & Jong, C. C. (2013). A memory-efficient scalable architecture for lifting-based discrete wavelet transform. IEEE transactions on circuits and systems II : express briefs, 60(8), 502-506.||Series/Report no.:||IEEE transactions on circuits and systems II : express briefs||Abstract:||In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory efficiency and short critical path. The memory efficiency is achieved with a novel scanning method that enables tradeoff of external memory bandwidth and on-chip memory. Based on the data flow graph of the flipped lifting algorithm, processing units (PUs) are developed for maximally utilizing the inherent parallelism. With S number of PUs, the throughput can be scaled while keeping the latency constant. Compared with the best existing architecture, the proposed architecture requires less memory. For an N × N image, the proposed architecture consumes a total of only 3N + 24S words of transposition memory, temporal memory, and pipeline registers. The synthesized results in a 90-nm CMOS process show that it achieves better area-delay products than the best existing design by 32.3%, 31.5%, and 27.0% when S = 2, 4, and 8, respectively, and by 26%, 26%, and 22% when the overhead for buffering the required overlapped pixels is taken into account.||URI:||https://hdl.handle.net/10356/102401
|ISSN:||1549-7747||DOI:||http://dx.doi.org/10.1109/TCSII.2013.2268335||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Journal Articles|
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