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|Title:||A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels||Authors:||Lim, Melvin Heng Li
Goh, Wang Ling
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2012||Source:||Lim, M. H. L., Goh, W. L., & Qin, Z. (2012). A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels. 2012 International Symposium on Intelligent Signal Processing and Communications Systems, 760-765.||Abstract:||The scrutiny of the class of Reed-Solomon (RS) based quasi-cyclic (QC) low-density parity-check (LDPC) codes has inspired the authors to propose a memory efficient mirror-paradigm (MP) RS-based QC-LDPC code by exploiting the geometrical properties from the RS-based QC-LDPC nomenclature. Without any loss in performance, the proposed MPRS-based QC-LDPC code delivers discernible memory savings that address the concerns of hefty H-matrices associated to lengthy codewords for non-volatile memory (NVM) applications. Besides, the MPRS-based QC-LDPC codes are not confined to any particular hardware implementation and are compatible with various decoder architectures to complement other optimization schemes.||URI:||https://hdl.handle.net/10356/103596
|DOI:||http://dx.doi.org/10.1109/ISPACS.2012.6473593||Rights:||© 2012 IEEE||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Conference Papers|
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