dc.contributor.authorAgung, Alit Apriyana Anak
dc.contributor.authorZhang, Yue Ping
dc.date.accessioned2013-10-25T06:48:06Z
dc.date.available2013-10-25T06:48:06Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.citationAgung, A. A. A., & Zhang, Y. P. (2012). Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method. International Journal of RF and Microwave Computer-Aided Engineering, 22(3), 297-307.en_US
dc.identifier.urihttp://hdl.handle.net/10220/16915
dc.description.abstractThe multifingers' parasitic capacitances modeling of 65-nm CMOS transistors for millimeter-wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high-frequency structure simulator environment. The material properties of the devices as given by the foundry are used during simulation and then full electromagnetic simulations are carried out to extract the Y-parameters of the model. Unit-cell parameters extraction method is carried out in order to save memory and simulation time. In this case, the multifinger transistors are divided into unit-cells and then the parasitic capacitances of the unit-cells are calculated from the extracted Y-parameter. Based on linear scaling, the parasitic capacitance of the multifingers transistor can be obtained with good accuracy (less than 5% error).en_US
dc.language.isoenen_US
dc.relation.ispartofseriesInternational journal of RF and microwave computer-aided engineeringen_US
dc.rights© 2012 Wiley Periodicals, Inc.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering
dc.titleMultifingers capacitances modeling of 65-Nm CMOS transistor by unit cell methoden_US
dc.typeJournal Article
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1002/mmce.20576


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