Vertical silicon nanowire platform for low power electronics and clean energy applications
Kwong, Dim Lee
Chen, Z. X.
Wong, S. M.
Shen, N. S.
Yu, Y. H.
Lee, S. J.
Date of Issue2012
School of Electrical and Electronic Engineering
This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.
DRNTU::Engineering::Electrical and electronic engineering
Journal of nanotechnology
© 2012 The Authors. This paper was published in Journal of Nanotechnology and is made available as an electronic reprint (preprint) with permission of the authors. The paper can be found at the following official DOI: [http://dx.doi.org/10.1155/2012/492121]. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.