Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model
Tan, Chuan Seng
Lim, Sung Kyu
Date of Issue2013
Asia and South Pacific Design Automation Conference (18th : 2013 : Yokohama, Japan)
School of Electrical and Electronic Engineering
3D physical design needs accurate device model of through-silicon vias (TSVs). In this paper, physics-based electrical-thermal model is introduced for both signal and dummy thermal TSVs with the consideration of nonlinear electrical-thermal dependence. Taking thermal-reliable 3D clock-tree synthesis as a case-study to verify the effectiveness of the proposed TSV model, one nonlinear programming-based clock-skew reduction problem is formulated to allocate thermal TSVs for clock-skew reduction under non-uniform temperature distribution. With a number of 3D clock-tree benchmarks, experiments show that under the nonlinear electrical-thermal TSV model, insertion of thermal TSVs can effectively reduce temperature-gradient introduced clock-skew by 58.4% on average, and has 11.6% higher clock-skew reduction than the result under linear electrical-thermal model.
DRNTU::Engineering::Electrical and electronic engineering
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