Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/99797
Title: Design of LUT based RNS reverse converters
Authors: Kong, Wei Lam
Vun, Chan Hua
Keywords: DRNTU::Engineering::Computer science and engineering
Issue Date: 2013
Source: Kong, W. L., & Vun, C. H. (2013). Design of LUT based RNS reverse converters. 2013 IEEE International Symposium on Consumer Electronics (ISCE), pp119-120.
Abstract: This paper presents the strategies to implement Residue Number System reverse converter based on the Look-Up Table (LUT) approach that is applicable for general moduli set. The approach makes use of partitioning to divide the LUT entries into multiple small LUTs in parallel, where their outputs can be further selected to obtain the equivalent binary number. Pipelining architecture is also incorporated to improve the operation speed. These techniques are hence suitable for general moduli set with large moduli value. Implementation results based on FPGA further demonstrate the feasibility and effectiveness of the proposed approach.
URI: https://hdl.handle.net/10356/99797
http://hdl.handle.net/10220/17352
DOI: 10.1109/ISCE.2013.6570139
Rights: © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Published version is available at http://dx.doi.org/10.1109/ISCE.2013.6570139 .
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Conference Papers

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